<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">        radix dec
global__variables__bank0 equ 32
global__variables__bank1 equ 160
global__variables__bank2 equ 288
global__variables__bank3 equ 496
global__bit__variables__bank0 equ 61
global__bit__variables__bank1 equ 160
global__bit__variables__bank2 equ 288
global__bit__variables__bank3 equ 496
indf___register equ 0
pcl___register equ 2
c___byte equ 3
c___bit equ 0
z___byte equ 3
z___bit equ 2
rp0___byte equ 3
rp0___bit equ 5
rp1___byte equ 3
rp1___bit equ 6
irp___byte equ 3
irp___bit equ 7
trisa___register equ 0x85
trisb___register equ 0x86
fsr___register equ 4
pclath___register equ 10
        org 0
start:
        nop
        nop
        nop
        goto skip___interrupt
interrupt___vector:
        retfie
skip___interrupt:
        ; Initialize A/D system to allow digital I/O
        movlw 3
        movwf 31
        ; Initialize TRIS registers
        movlw 131
        ; Switch from register bank 0 to register bank 1 (which contains trisa___register)
        bsf rp0___byte,rp0___bit
        ; Register bank is now 1
        movwf trisa___register
        movlw 15
        movwf trisb___register
        clrf pclath___register
        ; Switch from register bank 1 to register bank 0
        bcf rp0___byte,rp0___bit
        ; Register bank is now 0
        goto main
        ; comment #############################################################################
        ; comment {}
        ; comment {Copyright &lt; c &gt; 2002 by Wayne C . Gramlich .}
        ; comment {All rights reserved .}
        ; comment {}
        ; comment {Permission to use , copy , modify , distribute , and sell this software}
        ; comment {for any purpose is hereby granted without fee provided that the above}
        ; comment {copyright notice and this permission are retained . The author makes}
        ; comment {no representations about the suitability of this software for any purpose .}
        ; comment {It is provided { as is } without express or implied warranty .}
        ; comment {}
        ; comment {This is control microcode for Wayne ' s motion CNC board at :}
        ; comment {}
        ; comment {http : / / web . gramlich . net / projects / cnc / motion / index . html}
        ; comment {}
        ; comment {for more details .}
        ; comment {}
        ; comment {Some pin assignments :}
        ; comment {}
        ; comment {No Name Kind Description}
        ; comment {= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =}
        ; comment {1 RA2 / AN2 / VREF Digital Out DAC Chip Select}
        ; comment {2 RA3 / AN3 / CMP1 Digital Out Home Out *}
        ; comment {3 RA4 / TOCKI / CMP2 Digital In Home}
        ; comment {4 RA5 / MCLR * / THV Digital In Home In *}
        ; comment {5 VSS Ground Ground}
        ; comment {6 RB0 / INT Digital In Step}
        ; comment {7 RB1 / RX / DT Digital In Receive}
        ; comment {8 RB2 / TX / CK Digital Out Transmit}
        ; comment {9 RB3 / CCP1 Digital In Direction}
        ; comment {10 RB4 / PGM Digital Out Phase 1}
        ; comment {11 RB5 Digital Out Phase 2}
        ; comment {12 RB6 / T1OSO / TICK1 Digital Out Phase 0}
        ; comment {13 RB7 / T1OSI Digital Out Serial Clock}
        ; comment {14 VDD Power + 5 Volts}
        ; comment {15 RA6 / OSC2 / CLKOUT Digital Out Serial Data}
        ; comment {16 RA7 / OSC1 / CLKIN Digital In Oscillator}
        ; comment {17 RA0 / AN0 Digital In Encoder 0}
        ; comment {18 RA1 / AN1 Digital In Encoder 1}
        ; comment {}
        ; comment #############################################################################
        ;   processor pic16f628 cp = off cpd = off lvp = off bowden = off mclre = off pwrte = off wdte = off fosc = ec  
        ; 16139=0x3f0b 8199=0x2007
        __config 16139
configuration___address equ 8199
        ;   constant clock_rate 20000000  
clock_rate equ 20000000
        ; comment {Some character constants :}
        ;   constant sp 32  
sp equ 32
        ;   constant cr 13  
cr equ 13
        ;   constant lf 10  
lf equ 10
        ; comment {Some register definitions :}
tmr0 equ 1
status equ 3
        ;   bind c status @ 0  
c equ status+0
c__byte equ status+0
c__bit equ 0
        ;   bind z status @ 2  
z equ status+0
z__byte equ status+0
z__bit equ 2
intcon equ 11
        ;   bind gie intcon @ 7  
gie equ intcon+0
gie__byte equ intcon+0
gie__bit equ 7
        ;   bind t0ie intcon @ 5  
t0ie equ intcon+0
t0ie__byte equ intcon+0
t0ie__bit equ 5
        ;   bind inte intcon @ 4  
inte equ intcon+0
inte__byte equ intcon+0
inte__bit equ 4
        ;   bind rbie intcon @ 3  
rbie equ intcon+0
rbie__byte equ intcon+0
rbie__bit equ 3
        ;   bind t0if intcon @ 2  
t0if equ intcon+0
t0if__byte equ intcon+0
t0if__bit equ 2
        ;   bind intf intcon @ 1  
intf equ intcon+0
intf__byte equ intcon+0
intf__bit equ 1
        ;   bind rbif intcon @ 0  
rbif equ intcon+0
rbif__byte equ intcon+0
rbif__bit equ 0
pir1 equ 12
        ;   bind eeif pir1 @ 7  
eeif equ pir1+0
eeif__byte equ pir1+0
eeif__bit equ 7
        ;   bind cmif pir1 @ 6  
cmif equ pir1+0
cmif__byte equ pir1+0
cmif__bit equ 6
        ;   bind rcif pir1 @ 5  
rcif equ pir1+0
rcif__byte equ pir1+0
rcif__bit equ 5
        ;   bind txif pir1 @ 4  
txif equ pir1+0
txif__byte equ pir1+0
txif__bit equ 4
        ;   bind ccp1if pir1 @ 2  
ccp1if equ pir1+0
ccp1if__byte equ pir1+0
ccp1if__bit equ 2
        ;   bind tmr2if pir1 @ 1  
tmr2if equ pir1+0
tmr2if__byte equ pir1+0
tmr2if__bit equ 1
        ;   bind tmr1if pir1 @ 0  
tmr1if equ pir1+0
tmr1if__byte equ pir1+0
tmr1if__bit equ 0
rcsta equ 24
        ;   bind spen rcsta @ 7  
spen equ rcsta+0
spen__byte equ rcsta+0
spen__bit equ 7
        ;   bind rx9 rcsta @ 6  
rx9 equ rcsta+0
rx9__byte equ rcsta+0
rx9__bit equ 6
        ;   bind sren rcsta @ 5  
sren equ rcsta+0
sren__byte equ rcsta+0
sren__bit equ 5
        ;   bind cren rcsta @ 4  
cren equ rcsta+0
cren__byte equ rcsta+0
cren__bit equ 4
        ;   bind aden rcsta @ 3  
aden equ rcsta+0
aden__byte equ rcsta+0
aden__bit equ 3
        ;   bind ferr rcsta @ 2  
ferr equ rcsta+0
ferr__byte equ rcsta+0
ferr__bit equ 2
        ;   bind oerr rcsta @ 1  
oerr equ rcsta+0
oerr__byte equ rcsta+0
oerr__bit equ 1
        ;   bind rx9d rcsta @ 0  
rx9d equ rcsta+0
rx9d__byte equ rcsta+0
rx9d__bit equ 0
txreg equ 25
rcreg equ 26
        ; comment {Comparator module control :}
cmcon equ 31
        ;   bind c2out cmcon @ 7  
c2out equ cmcon+0
c2out__byte equ cmcon+0
c2out__bit equ 7
        ;   bind c1out cmcon @ 6  
c1out equ cmcon+0
c1out__byte equ cmcon+0
c1out__bit equ 6
        ;   bind c2inv cmcon @ 5  
c2inv equ cmcon+0
c2inv__byte equ cmcon+0
c2inv__bit equ 5
        ;   bind c1inv cmcon @ 4  
c1inv equ cmcon+0
c1inv__byte equ cmcon+0
c1inv__bit equ 4
        ;   bind cis cmcon @ 3  
cis equ cmcon+0
cis__byte equ cmcon+0
cis__bit equ 3
        ;   bind cm2 cmcon @ 2  
cm2 equ cmcon+0
cm2__byte equ cmcon+0
cm2__bit equ 2
        ;   bind cm1 cmcon @ 1  
cm1 equ cmcon+0
cm1__byte equ cmcon+0
cm1__bit equ 1
        ;   bind cm0 cmcon @ 0  
cm0 equ cmcon+0
cm0__byte equ cmcon+0
cm0__bit equ 0
option equ 129
        ;   bind t0cs option @ 5  
t0cs equ option+0
t0cs__byte equ option+0
t0cs__bit equ 5
        ;   bind t0se option @ 4  
t0se equ option+0
t0se__byte equ option+0
t0se__bit equ 4
        ;   bind psa option @ 3  
psa equ option+0
psa__byte equ option+0
psa__bit equ 3
        ;   bind ps2 option @ 2  
ps2 equ option+0
ps2__byte equ option+0
ps2__bit equ 2
        ;   bind ps1 option @ 1  
ps1 equ option+0
ps1__byte equ option+0
ps1__bit equ 1
        ;   bind ps0 option @ 0  
ps0 equ option+0
ps0__byte equ option+0
ps0__bit equ 0
pie1 equ 140
        ;   bind eeie pie1 @ 7  
eeie equ pie1+0
eeie__byte equ pie1+0
eeie__bit equ 7
        ;   bind cmie pie1 @ 6  
cmie equ pie1+0
cmie__byte equ pie1+0
cmie__bit equ 6
        ;   bind rcie pie1 @ 5  
rcie equ pie1+0
rcie__byte equ pie1+0
rcie__bit equ 5
        ;   bind txie pie1 @ 4  
txie equ pie1+0
txie__byte equ pie1+0
txie__bit equ 4
        ;   bind ccp1ie pie1 @ 2  
ccp1ie equ pie1+0
ccp1ie__byte equ pie1+0
ccp1ie__bit equ 2
        ;   bind tmr2ie pie1 @ 1  
tmr2ie equ pie1+0
tmr2ie__byte equ pie1+0
tmr2ie__bit equ 1
        ;   bind tmr1ie pie1 @ 0  
tmr1ie equ pie1+0
tmr1ie__byte equ pie1+0
tmr1ie__bit equ 0
txsta equ 152
        ;   bind tx9 txsta @ 6  
tx9 equ txsta+0
tx9__byte equ txsta+0
tx9__bit equ 6
        ;   bind txen txsta @ 5  
txen equ txsta+0
txen__byte equ txsta+0
txen__bit equ 5
        ;   bind sync txsta @ 4  
sync equ txsta+0
sync__byte equ txsta+0
sync__bit equ 4
        ;   bind brgh txsta @ 2  
brgh equ txsta+0
brgh__byte equ txsta+0
brgh__bit equ 2
        ;   bind trmt txsta @ 1  
trmt equ txsta+0
trmt__byte equ txsta+0
trmt__bit equ 1
        ;   bind tx9d txsta @ 0  
tx9d equ txsta+0
tx9d__byte equ txsta+0
tx9d__bit equ 0
spbrg equ 153
        ; comment {Some port , bit , and pin definitions :}
        ; comment {Port A pin assignments :}
        ; comment {RA0 : Encoder 0}
        ; comment {RA1 : Encoder 1}
        ; comment {RA2 : DAC Chip Select}
        ; comment {RA3 : Home Out}
        ; comment {RA4 : Home}
        ; comment {RA5 : Home In}
        ; comment {RA6 : Serial Data}
        ; comment {RA7 : Oscillator In}
        ;   constant encoder0_bit 0  
encoder0_bit equ 0
        ;   constant encoder1_bit 1  
encoder1_bit equ 1
        ;   constant dac_select_bit 2  
dac_select_bit equ 2
        ;   constant home_out_bit 3  
home_out_bit equ 3
        ;   constant home_bit 4  
home_bit equ 4
        ;   constant home_in_bit 5  
home_in_bit equ 5
        ;   constant serial_data_bit 6  
serial_data_bit equ 6
        ;   constant osc_in_bit 7  
osc_in_bit equ 7
porta equ 5
encoder0__byte equ 5
encoder0__bit equ 0
encoder1__byte equ 5
encoder1__bit equ 1
dac_select__byte equ 5
dac_select__bit equ 2
home_out_bit__byte equ 5
home_out_bit__bit equ 3
home_bit__byte equ 5
home_bit__bit equ 4
home_in__byte equ 5
home_in__bit equ 5
serial_data__byte equ 5
serial_data__bit equ 6
osc_in__byte equ 5
osc_in__bit equ 7
        ; comment {Port B pin assignments :}
        ; comment {RB0 : Step}
        ; comment {RB1 : Serial Input &lt; RX &gt;}
        ; comment {RB2 : Serial Output &lt; TX &gt;}
        ; comment {RB3 : Direction}
        ; comment {RB4 : Phase 1}
        ; comment {RB5 : Phase 2}
        ; comment {RB6 : Phase 0}
        ; comment {RB7 : Serial Clock}
        ;   constant step_bit 0  
step_bit equ 0
        ;   constant rx_bit 1  
rx_bit equ 1
        ;   constant tx_bit 2  
tx_bit equ 2
        ;   constant direction_bit 3  
direction_bit equ 3
        ;   constant phase1_bit 4  
phase1_bit equ 4
        ;   constant phase2_bit 5  
phase2_bit equ 5
        ;   constant phase0_bit 6  
phase0_bit equ 6
        ;   constant serial_clock_bit 7  
serial_clock_bit equ 7
portb equ 6
step__byte equ 6
step__bit equ 0
        ; comment {When using the USART , both the TX and RX pins must be set to input :}
tx_pin__byte equ 6
tx_pin__bit equ 2
rx_pin__byte equ 6
rx_pin__bit equ 1
direction__byte equ 6
direction__bit equ 3
phase1__byte equ 6
phase1__bit equ 4
phase2__byte equ 6
phase2__bit equ 5
phase0__byte equ 6
phase0__bit equ 6
serial_clock__byte equ 6
serial_clock__bit equ 7
        ; string_constants Start
string___fetch:
        movwf pcl___register
        ;   hello_string = 0s'Ctrl'  
hello_string___string equ 0
hello_string:
        addwf pcl___register,f
        ; Length = 4
        retlw 4
        ; `Ctrl'
        retlw 67
        retlw 116
        retlw 114
        retlw 108
        ; string__constants End
send_in_index equ global__variables__bank0+0
send_out_index equ global__variables__bank0+1
        ;   constant send_buffer_size 10  
send_buffer_size equ 10
send_buffer equ global__variables__bank0+2

        ; procedure main start
main:
main__variables__base equ global__variables__bank0+12
main__bytes__base equ main__variables__base+0
main__bits__base equ main__variables__base+6
main__total__bytes equ 6
main__287byte0 equ main__bytes__base+5
        ;   arguments_none  
main__char equ main__bytes__base+0
main__coil_a equ main__bytes__base+1
main__coil_b equ main__bytes__base+2
main__number equ main__bytes__base+3
main__phase equ main__bytes__base+4
        ; Get all interrupts turned off :
        ;   intcon := 0  
        clrf intcon
        ;   pie1 := 0  
        ; Switch from register bank 0 to register bank 1 (which contains pie1)
        bsf rp0___byte,rp0___bit
        ; Register bank is now 1
        clrf pie1
        ;   pir1 := 0  
        ; Switch from register bank 1 to register bank 0 (which contains pir1)
        bcf rp0___byte,rp0___bit
        ; Register bank is now 0
        clrf pir1
        ; Initialize UART :
        ; Prescaler = low :
        ; brgh := 0
        ; Prescaler = high
        ;   brgh := 1  
        ; Switch from register bank 0 to register bank 1 (which contains brgh__byte)
        bsf rp0___byte,rp0___bit
        ; Register bank is now 1
        bsf brgh__byte,brgh__bit
        ; Baud rate = 2400 baud :
        ; spbrg := 129
        ; Baud rate = 115200 baud :
        ;   spbrg := 10  
        movlw 10
        movwf spbrg
        ; Asynchronous mode :
        ;   sync := 0  
        bcf sync__byte,sync__bit
        ; 8 - bit mode :
        ;   tx9 := 0  
        bcf tx9__byte,tx9__bit
        ; Serial Port Enable :
        ;   spen := 1  
        ; Switch from register bank 1 to register bank 0 (which contains spen__byte)
        bcf rp0___byte,rp0___bit
        ; Register bank is now 0
        bsf spen__byte,spen__bit
        ; Keep interrupts off :
        ;   txie := 0  
        ; Switch from register bank 0 to register bank 1 (which contains txie__byte)
        bsf rp0___byte,rp0___bit
        ; Register bank is now 1
        bcf txie__byte,txie__bit
        ; Clear out an previous character .
        ;   txif := 0  
        ; Switch from register bank 1 to register bank 0 (which contains txif__byte)
        bcf rp0___byte,rp0___bit
        ; Register bank is now 0
        bcf txif__byte,txif__bit
        ; Enable the transmitter :
        ;   txen := 1  
        ; Switch from register bank 0 to register bank 1 (which contains txen__byte)
        bsf rp0___byte,rp0___bit
        ; Register bank is now 1
        bsf txen__byte,txen__bit
        ; Enable the receiver :
        ; Keep inerrupts off :
        ;   rcie := 0  
        bcf rcie__byte,rcie__bit
        ; Enable continuous reception :
        ;   cren := 1  
        ; Switch from register bank 1 to register bank 0 (which contains cren__byte)
        bcf rp0___byte,rp0___bit
        ; Register bank is now 0
        bsf cren__byte,cren__bit
        ; Enable single receptions :
        ;   sren := 1  
        bsf sren__byte,sren__bit
        ; Disable address
        ;   aden := 0  
        bcf aden__byte,aden__bit
        ; Initialize the comparator module :
        ; Two independent comparators :
        ; cmcon := 4
        ; Initialize the timer module :
        ;   t0cs := 0  
        ; Switch from register bank 0 to register bank 1 (which contains t0cs__byte)
        bsf rp0___byte,rp0___bit
        ; Register bank is now 1
        bcf t0cs__byte,t0cs__bit
        ;   psa := 0  
        bcf psa__byte,psa__bit
        ;   ps2 := 1  
        bsf ps2__byte,ps2__bit
        ;   ps1 := 1  
        bsf ps1__byte,ps1__bit
        ;   ps0 := 1  
        bsf ps0__byte,ps0__bit
        ; Initialize ring buffer :
        ;   send_in_index := 0  
        ; Switch from register bank 1 to register bank 0 (which contains send_in_index)
        bcf rp0___byte,rp0___bit
        ; Register bank is now 0
        clrf send_in_index
        ;   send_out_index := 0  
        clrf send_out_index
        ; A little initialization :
        ;   number := 0  
        clrf main__number
        ;   phase := 0  
        clrf main__phase
        ;   dac_select := 1  
        bsf dac_select__byte,dac_select__bit
        ;   serial_clock := 0  
        bcf serial_clock__byte,serial_clock__bit
        ;   serial_data := 0  
        bcf serial_data__byte,serial_data__bit
        ;   call send_dac {{ 9 , 127 }}  
        movlw 9
        movwf send_dac__byte0
        movlw 127
        movwf send_dac__byte1
        call send_dac
        ;   call send_dac {{ 10 , 127 }}  
        movlw 10
        movwf send_dac__byte0
        movlw 127
        movwf send_dac__byte1
        call send_dac
        ; Main loop
        ; loop_forever ... start
main__273loop__forever:
        ; See whether we can transmit a character :
        ; if { send_in_index != send_out_index &amp;&amp; txif } start
        movf send_in_index,w
        subwf send_out_index,w
        ; expression=`send_in_index != send_out_index' exp_delay=2 true_delay=-1  false_delay=2 true_size=13 false_size=1
        btfsc z___byte,z___bit
        goto and275__0false
        ; expression=`txif' exp_delay=0 true_delay=11  false_delay=0 true_size=11 false_size=0
        btfss txif__byte,txif__bit
        goto label275__1end
and275__0true:
        ; if { send_in_index != send_out_index &amp;&amp; txif } body start
        ;   txreg := send_buffer ~~ {{ send_out_index }}  
        movlw LOW send_buffer
        addwf send_out_index,w
        movwf fsr___register
        bcf irp___register,irp___bit
        movf indf___register,w
        movwf txreg
        ;   send_out_index := send_out_index + 1  
        incf send_out_index,f
        ; if { send_out_index &gt;= send_buffer_size } start
        movlw 10
        subwf send_out_index,w
        ; expression=`{ send_out_index &gt;= send_buffer_size }' exp_delay=2 true_delay=1  false_delay=0 true_size=1 false_size=0
        btfsc c___byte,c___bit
        ; if { send_out_index &gt;= send_buffer_size } body start
        ;   send_out_index := 0  
        clrf send_out_index
        ; if { send_out_index &gt;= send_buffer_size } body end
        ; if exp=` send_out_index &gt;= send_buffer_size ' false skip delay=4
        ; Other expression=`{ send_out_index &gt;= send_buffer_size }' delay=4
        ; if { send_out_index &gt;= send_buffer_size } end
        ; if { send_in_index != send_out_index &amp;&amp; txif } body end
label275__1end:
        ; if exp=`txif' empty false
        ; Other expression=`txif' delay=-1
        ; if exp=`send_in_index != send_out_index' false goto
        ; Other expression=`send_in_index != send_out_index' delay=-1
and275__0false:
and275__0end:
        ; if { send_in_index != send_out_index &amp;&amp; txif } end
        ; See whether we ' ve got a character :
        ; if { rcif } start
        ; expression=`{ rcif }' exp_delay=0 true_delay=-1  false_delay=0 true_size=61 false_size=0
        btfss rcif__byte,rcif__bit
        goto label284__0end
        ; if { rcif } body start
        ;   char := rcreg  
        movf rcreg,w
        movwf main__char
        ; if { {{ 0c'0' &lt;= char &amp;&amp; char &lt;= 0c'7' }} } start
        movlw 48
        subwf main__char,w
        ; expression=`0c'0' &lt;= char' exp_delay=2 true_delay=-1  false_delay=1 true_size=55 false_size=1
        btfss c___byte,c___bit
        goto and286__0false
        movlw 56
        subwf main__char,w
        ; expression=`char &lt;= 0c'7'' exp_delay=2 true_delay=8  false_delay=-1 true_size=8 false_size=42
        btfsc c___byte,c___bit
        goto label286__1false
label286__1true:
and286__0true:
        ; if { {{ 0c'0' &lt;= char &amp;&amp; char &lt;= 0c'7' }} } body start
        ;   number := {{ number &lt;&lt; 3 }} + char - 0c'0'  
        rlf main__number,w
        movwf main__287byte0
        rlf main__287byte0,f
        rlf main__287byte0,w
        andlw 248
        addwf main__char,w
        addlw 208
        movwf main__number
        ; if { {{ 0c'0' &lt;= char &amp;&amp; char &lt;= 0c'7' }} } body end
        goto label286__1end
label286__1false:
and286__0false:
        ; else body start
        ; if { char = 0c'X' } start
        movlw 88
        subwf main__char,w
        ; expression=`{ char = 0c'X' }' exp_delay=2 true_delay=2  false_delay=-1 true_size=4 false_size=32
        btfsc z___byte,z___bit
        goto label289__0true
label289__0false:
        movlw 120
        subwf main__char,w
        ; expression=`{ char = 0c'x' }' exp_delay=2 true_delay=2  false_delay=-1 true_size=4 false_size=23
        btfsc z___byte,z___bit
        goto label292__0true
label292__0false:
        movlw 97
        subwf main__char,w
        ; expression=`{ char = 0c'a' }' exp_delay=2 true_delay=5  false_delay=-1 true_size=7 false_size=11
        btfsc z___byte,z___bit
        goto label295__0true
label295__0false:
        movlw 98
        subwf main__char,w
        ; expression=`{ char = 0c'b' }' exp_delay=2 true_delay=5  false_delay=0 true_size=7 false_size=0
        btfss z___byte,z___bit
        goto label298__0end
        ; else_if { char = 0c'b' } body start
        ;   coil_b := number  
        movf main__number,w
        movwf main__coil_b
        ;   call send_dac {{ 10 , coil_b }}  
        movlw 10
        movwf send_dac__byte0
        movf main__coil_b,w
        movwf send_dac__byte1
        call send_dac
        ; else_if { char = 0c'b' } body end
label298__0end:
        ; if exp=` char = 0c'b' ' empty false
        ; Other expression=`{ char = 0c'b' }' delay=-1
        goto label295__0end
label295__0true:
        ; else_if { char = 0c'a' } body start
        ;   coil_a := number  
        movf main__number,w
        movwf main__coil_a
        ;   call send_dac {{ 9 , coil_a }}  
        movlw 9
        movwf send_dac__byte0
        movf main__coil_a,w
        movwf send_dac__byte1
        call send_dac
        ; else_if { char = 0c'a' } body end
        ; if exp=` char = 0c'a' ' generic
label295__0end:
        ; Other expression=`{ char = 0c'a' }' delay=-1
        goto label292__0end
label292__0true:
        ; else_if { char = 0c'x' } body start
        ;   phase := phase + 1  
        incf main__phase,f
        ;   call send_byte {{ char }}  
        movf main__char,w
        movwf send_byte__character
        call send_byte
        ; else_if { char = 0c'x' } body end
        ; if exp=` char = 0c'x' ' generic
label292__0end:
        ; Other expression=`{ char = 0c'x' }' delay=-1
        goto label289__0end
label289__0true:
        ; if { char = 0c'X' } body start
        ;   phase := phase - 1  
        decf main__phase,f
        ;   call send_byte {{ char }}  
        movf main__char,w
        movwf send_byte__character
        call send_byte
        ; if { char = 0c'X' } body end
        ; if exp=` char = 0c'X' ' generic
label289__0end:
        ; Other expression=`{ char = 0c'X' }' delay=-1
        ; if { char = 0c'X' } end
        ;   number := 0  
        clrf main__number
        ; else body end
        ; if exp=`char &lt;= 0c'7'' generic
label286__1end:
        ; Other expression=`char &lt;= 0c'7'' delay=-1
        ; if exp=`0c'0' &lt;= char' false goto
        ; Other expression=`0c'0' &lt;= char' delay=-1
and286__0end:
        ; if { {{ 0c'0' &lt;= char &amp;&amp; char &lt;= 0c'7' }} } end
        ; if { rcif } body end
label284__0end:
        ; if exp=`rcif' empty false
        ; Other expression=`{ rcif }' delay=-1
        ; if { rcif } end
        ; Output the phase :
        ; if { phase @ 2 } start
        ; Alias variable for select phase @ 2
main__phase__307select0 equ main__phase+0
main__phase__307select0__byte equ main__phase+0
main__phase__307select0__bit equ 2
        ; expression=`{ phase @ 2 }' exp_delay=0 true_delay=1  false_delay=1 true_size=1 false_size=1
        btfsc main__phase__307select0__byte,main__phase__307select0__bit
        ; if { phase @ 2 } body start
        ;   phase2 := 1  
        bsf phase2__byte,phase2__bit
        ; if { phase @ 2 } body end
        btfss main__phase__307select0__byte,main__phase__307select0__bit
        ; else body start
        ;   phase2 := 0  
        bcf phase2__byte,phase2__bit
        ; else body end
        ; if exp=` phase @ 2 ' single true and false skip delay=4
        ; Other expression=`{ phase @ 2 }' delay=4
        ; if { phase @ 2 } end
        ; if { phase @ 1 } start
        ; Alias variable for select phase @ 1
main__phase__312select0 equ main__phase+0
main__phase__312select0__byte equ main__phase+0
main__phase__312select0__bit equ 1
        ; expression=`{ phase @ 1 }' exp_delay=0 true_delay=1  false_delay=1 true_size=1 false_size=1
        btfsc main__phase__312select0__byte,main__phase__312select0__bit
        ; if { phase @ 1 } body start
        ;   phase1 := 1  
        bsf phase1__byte,phase1__bit
        ; if { phase @ 1 } body end
        btfss main__phase__312select0__byte,main__phase__312select0__bit
        ; else body start
        ;   phase1 := 0  
        bcf phase1__byte,phase1__bit
        ; else body end
        ; if exp=` phase @ 1 ' single true and false skip delay=4
        ; Other expression=`{ phase @ 1 }' delay=4
        ; if { phase @ 1 } end
        ; if { phase @ 0 } start
        ; Alias variable for select phase @ 0
main__phase__317select0 equ main__phase+0
main__phase__317select0__byte equ main__phase+0
main__phase__317select0__bit equ 0
        ; expression=`{ phase @ 0 }' exp_delay=0 true_delay=1  false_delay=1 true_size=1 false_size=1
        btfsc main__phase__317select0__byte,main__phase__317select0__bit
        ; if { phase @ 0 } body start
        ;   phase0 := 1  
        bsf phase0__byte,phase0__bit
        ; if { phase @ 0 } body end
        btfss main__phase__317select0__byte,main__phase__317select0__bit
        ; else body start
        ;   phase0 := 0  
        bcf phase0__byte,phase0__bit
        ; else body end
        ; if exp=` phase @ 0 ' single true and false skip delay=4
        ; Other expression=`{ phase @ 0 }' delay=4
        ; if { phase @ 0 } end
        goto main__273loop__forever
        ; loop_forever ... end
        ; procedure main end
        ; comment {DAC routines :}

        ; procedure send_dac start
send_dac:
send_dac__variables__base equ global__variables__bank0+18
send_dac__bytes__base equ send_dac__variables__base+0
send_dac__bits__base equ send_dac__variables__base+2
send_dac__total__bytes equ 2
send_dac__byte0 equ send_dac__bytes__base+0
send_dac__byte1 equ send_dac__bytes__base+1
        ; This procedure will output &lt; byte0 &gt; followed by &lt; byte1 &gt; to the
        ; Digital to Analog converter .
        ;   dac_select := 0  
        bcf dac_select__byte,dac_select__bit
        ;   call send_dac_byte {{ byte0 }}  
        movf send_dac__byte0,w
        movwf send_dac_byte__dac
        call send_dac_byte
        ;   call send_dac_byte {{ byte1 }}  
        movf send_dac__byte1,w
        movwf send_dac_byte__dac
        call send_dac_byte
        ;   dac_select := 1  
        bsf dac_select__byte,dac_select__bit
        ; procedure send_dac end
        retlw 0

        ; procedure send_dac_byte start
send_dac_byte:
send_dac_byte__variables__base equ global__variables__bank0+20
send_dac_byte__bytes__base equ send_dac_byte__variables__base+0
send_dac_byte__bits__base equ send_dac_byte__variables__base+2
send_dac_byte__total__bytes equ 2
send_dac_byte__dac equ send_dac_byte__bytes__base+0
send_dac_byte__count equ send_dac_byte__bytes__base+1
        ; `count_down count 8 ...' start
        movlw 8
        movwf send_dac_byte__count
send_dac_byte__347_loop:
        ;   serial_data := dac @ 7  
        ; Alias variable for select dac @ 7
send_dac_byte__dac__348select0 equ send_dac_byte__dac+0
send_dac_byte__dac__348select0__byte equ send_dac_byte__dac+0
send_dac_byte__dac__348select0__bit equ 7
        btfss send_dac_byte__dac__348select0__byte,send_dac_byte__dac__348select0__bit
        bcf serial_data__byte,serial_data__bit
        btfsc send_dac_byte__dac__348select0__byte,send_dac_byte__dac__348select0__bit
        bsf serial_data__byte,serial_data__bit
        ;   serial_clock := 1  
        bsf serial_clock__byte,serial_clock__bit
        ;   dac := dac &lt;&lt; 1  
        bcf c___byte,c___bit
        rlf send_dac_byte__dac,f
        ;   serial_clock := 0  
        bcf serial_clock__byte,serial_clock__bit
        decfsz send_dac_byte__count,f
        goto send_dac_byte__347_loop
send_dac_byte__347_done:
        ; `count_down count 8 ...' end
        ; procedure send_dac_byte end
        retlw 0
        ; comment {The following procedures are used to send data back to the master :}

        ; procedure send_byte start
send_byte:
send_byte__variables__base equ global__variables__bank0+22
send_byte__bytes__base equ send_byte__variables__base+0
send_byte__bits__base equ send_byte__variables__base+2
send_byte__total__bytes equ 2
send_byte__364byte0 equ send_byte__bytes__base+1
send_byte__character equ send_byte__bytes__base+0
        ; This procedure will cause &lt; character &gt; to placed into
        ; a ring buffer for transmission .
        ;   send_buffer ~~ {{ send_in_index }} := character  
        movf send_byte__character,w
        movwf send_byte__364byte0
        movlw LOW send_buffer
        addwf send_in_index,w
        movwf fsr___register
        movf send_byte__364byte0,w
        bcf irp___register,irp___bit
        movwf indf___register
        ;   send_in_index := send_in_index + 1  
        incf send_in_index,f
        ; if { send_in_index &gt;= send_buffer_size } start
        movlw 10
        subwf send_in_index,w
        ; expression=`{ send_in_index &gt;= send_buffer_size }' exp_delay=2 true_delay=1  false_delay=0 true_size=1 false_size=0
        btfsc c___byte,c___bit
        ; if { send_in_index &gt;= send_buffer_size } body start
        ;   send_in_index := 0  
        clrf send_in_index
        ; if { send_in_index &gt;= send_buffer_size } body end
        ; if exp=` send_in_index &gt;= send_buffer_size ' false skip delay=4
        ; Other expression=`{ send_in_index &gt;= send_buffer_size }' delay=4
        ; if { send_in_index &gt;= send_buffer_size } end
        ; procedure send_byte end
        retlw 0

        ; procedure send_crlf start
send_crlf:
send_crlf__variables__base equ global__variables__bank0+24
send_crlf__bytes__base equ send_crlf__variables__base+0
send_crlf__bits__base equ send_crlf__variables__base+0
send_crlf__total__bytes equ 0
        ;   arguments_none  
        ; This procedure will output a carriage - return line - feed
        ; to the master .
        ;   call send_byte {{ cr }}  
        movlw 13
        movwf send_byte__character
        call send_byte
        ;   call send_byte {{ lf }}  
        movlw 10
        movwf send_byte__character
        call send_byte
        ; procedure send_crlf end
        retlw 0

        ; procedure send_octal start
send_octal:
send_octal__variables__base equ global__variables__bank0+24
send_octal__bytes__base equ send_octal__variables__base+0
send_octal__bits__base equ send_octal__variables__base+2
send_octal__total__bytes equ 2
send_octal__390byte0 equ send_octal__bytes__base+1
send_octal__389byte0 equ send_octal__bytes__base+1
send_octal__number equ send_octal__bytes__base+0
        ; This procedure will output &lt; number &gt; in octal to the tx port .
        ; Output the character in octal :
        ;   call send_byte {{ {{ number &gt;&gt; 6 }} + 0c'0' }}  
        swapf send_octal__number,w
        movwf send_octal__389byte0
        rrf send_octal__389byte0,f
        rrf send_octal__389byte0,w
        andlw 3
        addlw 48
        movwf send_byte__character
        call send_byte
        ;   call send_byte {{ {{ {{ number &gt;&gt; 3 }} &amp; 7 }} + 0c'0' }}  
        rrf send_octal__number,w
        movwf send_octal__390byte0
        rrf send_octal__390byte0,f
        rrf send_octal__390byte0,w
        andlw 7
        addlw 48
        movwf send_byte__character
        call send_byte
        ;   call send_byte {{ {{ number &amp; 7 }} + 0c'0' }}  
        movlw 7
        andwf send_octal__number,w
        addlw 48
        movwf send_byte__character
        call send_byte
        ;   call send_byte {{ sp }}  
        movlw 32
        movwf send_byte__character
        call send_byte
        ; procedure send_octal end
        retlw 0

        ; procedure send_string start
send_string:
send_string__variables__base equ global__variables__bank0+26
send_string__bytes__base equ send_string__variables__base+0
send_string__bits__base equ send_string__variables__base+3
send_string__total__bytes equ 3
send_string__message equ send_string__bytes__base+0
        ; This procedure will output &lt; message &gt; .
send_string__size equ send_string__bytes__base+1
send_string__index equ send_string__bytes__base+2
        ;   index := 0  
        clrf send_string__index
        ; `while  index &lt; message . size  ...' start
send_string__405while__continue:
        clrf pclath___register
        movf send_string__message,w
        call string___fetch
        subwf send_string__index,w
        ; expression=` index &lt; message . size ' exp_delay=4 true_delay=7  false_delay=2 true_size=8 false_size=1
        btfsc c___byte,c___bit
        goto send_string__405while__break
        ;   call send_byte {{ message ~~ {{ index }} }}  
        incf send_string__index,w
        addwf send_string__message,w
        clrf pclath___register
        call string___fetch
        movwf send_byte__character
        call send_byte
        ;   index := index + 1  
        incf send_string__index,f
        goto send_string__405while__continue
        ; if exp=` index &lt; message . size ' false goto
        ; Other expression=` index &lt; message . size ' delay=-1
send_string__405while__break:
        ; `while  index &lt; message . size  ...' end
        ;   call send_byte {{ sp }}  
        movlw 32
        movwf send_byte__character
        call send_byte
        ; procedure send_string end
        retlw 0

        ; Register bank 0 used 29 bytes of 96 available bytes
        ; Register bank 1 used 0 bytes of 80 available bytes
        ; Register bank 2 used 0 bytes of 48 available bytes
        ; Register bank 3 used 0 bytes of 0 available bytes

        end

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