1 radix dec 2 0007 global__variables__bank0 equ 7 3 0030 global__variables__bank1 equ 48 4 0017 global__bit__variables__bank0 equ 23 5 003a global__bit__variables__bank1 equ 58 6 0000 indf___register equ 0 7 0002 pcl___register equ 2 8 0003 c___byte equ 3 9 0000 c___bit equ 0 10 0003 z___byte equ 3 11 0002 z___bit equ 2 12 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) 13 0004 rp0___byte equ 4 14 0005 rp0___bit equ 5 15 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) 16 0004 rp1___byte equ 4 17 0006 rp1___bit equ 6 18 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) 19 0003 pa0___byte equ 3 20 0005 pa0___bit equ 5 21 0004 fsr___register equ 4 22 org 0 23 start: 24 ; Use oscillator calibration value already in register W 25 000 025 movwf 5 26 ; Initialize TRIS registers 27 001 cda movlw 218 28 002 006 tris 6 29 ; Initialize OPTION register 30 003 cc0 movlw 192 31 004 002 option 32 ; Switch from register bank 0 to register bank 1 33 005 5a4 bsf rp0___byte,rp0___bit 34 ; Register bank is now 1 35 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 36 006 5a3 bsf pa0___byte,pa0___bit 37 007 a32 goto main 38 ; comment ############################################################################# 39 ; comment {} 40 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich & William T . Benson .} 41 ; comment {All rights reserved .} 42 ; comment {} 43 ; comment {Permission to use , copy , modify , distribute , and sell this software} 44 ; comment {for any purpose is hereby granted without fee provided that the above} 45 ; comment {copyright notice and this permission are retained . The author makes} 46 ; comment {no representations about the suitability of this software for any purpose .} 47 ; comment {It is provided { as is } without express or implied warranty .} 48 ; comment {} 49 ; comment {This is the code that implements the BIROD2 RoboBrick . Basically} 50 ; comment {it just waits for commands that come in at 2400 baud and responds} 51 ; comment {to them . See} 52 ; comment {} 53 ; comment {http : / / web . gramlich . net / projects / robobricks / birod2 / index . html} 54 ; comment {} 55 ; comment {for more details .} 56 ; comment {} 57 ; comment ############################################################################# 58 ; processor pic12c509 cp = off wdte = on mclre = off fosc = intrc 59 ; 14=0xe 4095=0xfff 60 __config 14 61 0fff configuration___address equ 4095 62 ; comment {define processor constants} 63 ; constant clock_rate 4000000 64 3d0900 clock_rate equ 4000000 65 ; constant clocks_per_instruction 4 66 0004 clocks_per_instruction equ 4 67 ; constant instruction_rate clock_rate / clocks_per_instruction 68 f4240 instruction_rate equ 1000000 69 ; comment {Define serial communication control constants :} 70 ; constant baud_rate 2400 71 0960 baud_rate equ 2400 72 ; constant instructions_per_bit instruction_rate / baud_rate 73 01a0 instructions_per_bit equ 416 74 ; constant delays_per_bit 3 75 0003 delays_per_bit equ 3 76 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 77 008a instructions_per_delay equ 138 78 ; constant extra_instructions_per_bit 9 79 0009 extra_instructions_per_bit equ 9 80 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 81 0003 extra_instructions_per_delay equ 3 82 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 83 0087 delay_instructions equ 135 84 ; comment {Register definitions :} 85 ; comment {Status register :} 86 0003 status equ 3 87 ; bind c status @ 0 88 0003 c equ status+0 89 0003 c__byte equ status+0 90 0000 c__bit equ 0 91 ; bind z status @ 2 92 0003 z equ status+0 93 0003 z__byte equ status+0 94 0002 z__bit equ 2 95 ; comment {OSCCAL register :} 96 0005 osccal equ 5 97 ; constant osccal_unit 4 98 0004 osccal_unit equ 4 99 ; comment {constant osccal_unit 0x10} 100 ; comment {Define I / O port bit assignments :} 101 0006 porta equ 6 102 0006 out0__byte equ 6 103 0000 out0__bit equ 0 104 0006 in0__byte equ 6 105 0001 in0__bit equ 1 106 0006 out1__byte equ 6 107 0002 out1__bit equ 2 108 0006 in1__byte equ 6 109 0003 in1__bit equ 3 110 0006 serial_in__byte equ 6 111 0004 serial_in__bit equ 4 112 0006 serial_out__byte equ 6 113 0005 serial_out__bit equ 5 114 ; string_constants Start 115 ; Switch from register bank 1 to register bank 0 116 008 4a4 bcf rp0___byte,rp0___bit 117 ; Register bank is now 0 118 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 119 009 4a3 bcf pa0___byte,pa0___bit 120 string___fetch: 121 00a 022 movwf pcl___register 122 ; id = 1 , 0 , 11 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 7 , 0s'BIROD2B' , 15 , 0s'Gramlich&Benson' 123 0000 id___string equ 0 124 id: 125 00b 1e2 addwf pcl___register,f 126 ; Length = 48 127 00c 830 retlw 48 128 ; 1 129 00d 801 retlw 1 130 ; 0 131 00e 800 retlw 0 132 ; 11 133 00f 80b retlw 11 134 ; 1 135 010 801 retlw 1 136 ; 0 137 011 800 retlw 0 138 ; 0 139 012 800 retlw 0 140 ; 0 141 013 800 retlw 0 142 ; 0 143 014 800 retlw 0 144 ; 0r'16' 145 015 80a retlw 10 ; random number 146 016 82e retlw 46 ; random number 147 017 83c retlw 60 ; random number 148 018 89c retlw 156 ; random number 149 019 819 retlw 25 ; random number 150 01a 87a retlw 122 ; random number 151 01b 80c retlw 12 ; random number 152 01c 8b8 retlw 184 ; random number 153 01d 866 retlw 102 ; random number 154 01e 8ae retlw 174 ; random number 155 01f 8f0 retlw 240 ; random number 156 020 8df retlw 223 ; random number 157 021 8c0 retlw 192 ; random number 158 022 826 retlw 38 ; random number 159 023 805 retlw 5 ; random number 160 024 83d retlw 61 ; random number 161 ; 7 162 025 807 retlw 7 163 ; `BIROD2B' 164 026 842 retlw 66 165 027 849 retlw 73 166 028 852 retlw 82 167 029 84f retlw 79 168 02a 844 retlw 68 169 02b 832 retlw 50 170 02c 842 retlw 66 171 ; 15 172 02d 80f retlw 15 173 ; `Gramlich&Benson' 174 02e 847 retlw 71 175 02f 872 retlw 114 176 030 861 retlw 97 177 031 86d retlw 109 178 032 86c retlw 108 179 033 869 retlw 105 180 034 863 retlw 99 181 035 868 retlw 104 182 036 826 retlw 38 183 037 842 retlw 66 184 038 865 retlw 101 185 039 86e retlw 110 186 03a 873 retlw 115 187 03b 86f retlw 111 188 03c 86e retlw 110 189 ; string__constants End 190 ; comment {Interrupt masks :} 191 0017 interrupt_enable equ global__bit__variables__bank0+0 192 0017 interrupt_enable__byte equ global__bit__variables__bank0+0 193 0000 interrupt_enable__bit equ 0 194 0017 interrupt_pending equ global__bit__variables__bank0+0 195 0017 interrupt_pending__byte equ global__bit__variables__bank0+0 196 0001 interrupt_pending__bit equ 1 197 0017 alternate equ global__bit__variables__bank0+0 198 0017 alternate__byte equ global__bit__variables__bank0+0 199 0002 alternate__bit equ 2 200 0017 receiving equ global__bit__variables__bank0+0 201 0017 receiving__byte equ global__bit__variables__bank0+0 202 0003 receiving__bit equ 3 203 ; comment {Various masks < low order two bits only > :} 204 0007 inputs equ global__variables__bank0+0 205 0008 enable equ global__variables__bank0+1 206 0009 complement equ global__variables__bank0+2 207 000a falling equ global__variables__bank0+3 208 000b high equ global__variables__bank0+4 209 000c low equ global__variables__bank0+5 210 000d raising equ global__variables__bank0+6 211 ; comment {For now put all the smaller routines first so that they can live} 212 ; comment {within the first 256 bytes of main memory . The PIC12C5xx chips} 213 ; comment {can only call routines that are within the first 256 bytes < i . e .} 214 ; comment {the first half > of the code page .} 215 ; bank 1 216 ; Default register bank is now 1 217 218 ; procedure get_byte start 219 get_byte: 220 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 221 ; Procedure must be called with PCLATH set to code bank 0 222 0030 get_byte__variables__base equ global__variables__bank1+0 223 0030 get_byte__bytes__base equ get_byte__variables__base+0 224 0033 get_byte__bits__base equ get_byte__variables__base+3 225 0003 get_byte__total__bytes equ 3 226 ; arguments_none 227 0030 get_byte__0return__byte equ get_byte__bytes__base+0 228 ; Wait for a character and return it . 229 ; The get_byte < > procedure only waits for 9 - 2 / 3 bits . That 230 ; way the next call to get_byte < > will sychronize on the start 231 ; bit instead of possibly starting a little later . 232 0031 get_byte__count equ get_byte__bytes__base+1 233 0032 get_byte__char equ get_byte__bytes__base+2 234 ; Wait for start bit : 235 ; receiving := 1 236 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 237 03d 4a4 bcf rp0___byte,rp0___bit 238 ; Register bank is now 0 239 03e 577 bsf receiving__byte,receiving__bit 240 ; `while serial_in ...' start 241 ; Switch from register bank 0 to register bank 1 242 03f 5a4 bsf rp0___byte,rp0___bit 243 ; Register bank is now 1 244 get_byte__101while__continue: 245 ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 246 040 786 btfss serial_in__byte,serial_in__bit 247 041 a46 goto get_byte__101while__break 248 ; call delay {{ }} 249 ; Switch from register bank 1 to register bank 0 250 042 4a4 bcf rp0___byte,rp0___bit 251 ; Register bank is now 0 252 043 997 call delay 253 ; Switch from register bank 0 to register bank 1 254 044 5a4 bsf rp0___byte,rp0___bit 255 ; Register bank is now 1 256 045 a40 goto get_byte__101while__continue 257 ; if exp=`serial_in' false goto 258 ; Other expression=`serial_in' delay=-1 259 get_byte__101while__break: 260 ; `while serial_in ...' end 261 ; Clear interrupt : 262 ; 1 cycle : 263 ; serial_out := 1 264 046 5a6 bsf serial_out__byte,serial_out__bit 265 ; Skip over start bit : 266 ; call delay {{ }} 267 ; Switch from register bank 1 to register bank 0 268 047 4a4 bcf rp0___byte,rp0___bit 269 ; Register bank is now 0 270 048 997 call delay 271 ; call delay {{ }} 272 049 997 call delay 273 ; call delay {{ }} 274 04a 997 call delay 275 ; Sample in the middle third of each data bit : 276 ; 1 cycle : 277 ; char := 0 278 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 279 04b 5a4 bsf rp0___byte,rp0___bit 280 ; Register bank is now 1 281 04c 072 clrf get_byte__char 282 ; 2 cycles to set up loop : 283 ; 1 + 1 + 2 = 4 284 ; nop extra_instructions_per_bit - 4 285 ; Delay 5 cycles 286 04d 000 nop 287 04e 000 nop 288 04f 000 nop 289 050 000 nop 290 051 000 nop 291 ; `count_down count 8 ...' start 292 052 c08 movlw 8 293 053 031 movwf get_byte__count 294 get_byte__120_loop: 295 ; call delay {{ }} 296 ; Switch from register bank 1 to register bank 0 297 054 4a4 bcf rp0___byte,rp0___bit 298 ; Register bank is now 0 299 055 997 call delay 300 ; 2 cycles : 301 ; char := char >> 1 302 056 403 bcf c___byte,c___bit 303 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 304 057 5a4 bsf rp0___byte,rp0___bit 305 ; Register bank is now 1 306 058 332 rrf get_byte__char,f 307 ; 2 cycles : 308 ; if { serial_in } start 309 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 310 059 686 btfsc serial_in__byte,serial_in__bit 311 ; if { serial_in } body start 312 ; char @ 7 := 1 313 ; Select char @ 7 314 0032 get_byte__char__126select0 equ get_byte__char+0 315 0032 get_byte__char__126select0__byte equ get_byte__char+0 316 0007 get_byte__char__126select0__bit equ 7 317 05a 5f2 bsf get_byte__char__126select0__byte,get_byte__char__126select0__bit 318 ; if { serial_in } body end 319 ; if exp=`serial_in' false skip delay=2 320 ; Other expression=`{ serial_in }' delay=2 321 ; if { serial_in } end 322 ; call delay {{ }} 323 ; Switch from register bank 1 to register bank 0 324 05b 4a4 bcf rp0___byte,rp0___bit 325 ; Register bank is now 0 326 05c 997 call delay 327 ; call delay {{ }} 328 05d 997 call delay 329 ; 3 cycles at end of loop : 330 ; nop extra_instructions_per_bit - 7 331 ; Delay 2 cycles 332 05e 000 nop 333 05f 000 nop 334 ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) 335 060 5a4 bsf rp0___byte,rp0___bit 336 ; Register bank is now 1 337 061 2f1 decfsz get_byte__count,f 338 062 a54 goto get_byte__120_loop 339 get_byte__120_done: 340 ; `count_down count 8 ...' end 341 ; Skip over 2 / 3 ' s of stop bit : 342 ; call delay {{ }} 343 ; Switch from register bank 1 to register bank 0 344 063 4a4 bcf rp0___byte,rp0___bit 345 ; Register bank is now 0 346 064 997 call delay 347 ; call delay {{ }} 348 065 997 call delay 349 ; return char 350 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 351 066 5a4 bsf rp0___byte,rp0___bit 352 ; Register bank is now 1 353 067 212 movf get_byte__char,w 354 068 030 movwf get_byte__0return__byte 355 069 800 retlw 0 356 ; procedure get_byte end 357 358 ; procedure send_byte start 359 send_byte: 360 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 361 ; Procedure must be called with PCLATH set to code bank 0 362 0033 send_byte__variables__base equ global__variables__bank1+3 363 0033 send_byte__bytes__base equ send_byte__variables__base+0 364 0035 send_byte__bits__base equ send_byte__variables__base+2 365 0002 send_byte__total__bytes equ 2 366 0033 send_byte__char equ send_byte__bytes__base+0 367 ; Send < char > to < tx > : 368 0034 send_byte__count equ send_byte__bytes__base+1 369 ; < receiving > will be 1 if the last get / put routine was a get . 370 ; Before we start transmitting a response back , we want to ensure 371 ; that there has been enough time to turn the line around . 372 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 373 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 374 ; for good measure . Technically , the second call to delay < > 375 ; is not really needed . 376 ; if { receiving } start 377 ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 378 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 379 06a 4a4 bcf rp0___byte,rp0___bit 380 ; Register bank is now 0 381 06b 443 bcf z___byte,z___bit 382 06c 677 btfsc receiving__byte,receiving__bit 383 06d 543 bsf z___byte,z___bit 384 ; Switch from register bank 0 to register bank 1 385 06e 5a4 bsf rp0___byte,rp0___bit 386 ; Register bank is now 1 387 06f 743 btfss z___byte,z___bit 388 070 a76 goto label156__0end 389 ; if { receiving } body start 390 ; receiving := 0 391 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 392 071 4a4 bcf rp0___byte,rp0___bit 393 ; Register bank is now 0 394 072 477 bcf receiving__byte,receiving__bit 395 ; call delay {{ }} 396 073 997 call delay 397 ; call delay {{ }} 398 074 997 call delay 399 ; if { receiving } body end 400 ; Switch from register bank 0 to register bank 1 401 075 5a4 bsf rp0___byte,rp0___bit 402 ; Register bank is now 1 403 label156__0end: 404 ; if exp=`receiving' empty false 405 ; Other expression=`{ receiving }' delay=-1 406 ; if { receiving } end 407 ; Send the start bit : 408 ; serial_out := 0 409 076 4a6 bcf serial_out__byte,serial_out__bit 410 ; call delay {{ }} 411 ; Switch from register bank 1 to register bank 0 412 077 4a4 bcf rp0___byte,rp0___bit 413 ; Register bank is now 0 414 078 997 call delay 415 ; call delay {{ }} 416 079 997 call delay 417 ; call delay {{ }} 418 07a 997 call delay 419 ; Send the data : 420 ; `count_down count 8 ...' start 421 07b c08 movlw 8 422 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 423 07c 5a4 bsf rp0___byte,rp0___bit 424 ; Register bank is now 1 425 07d 034 movwf send_byte__count 426 send_byte__169_loop: 427 ; 4 cycles : 428 ; serial_out := char @ 0 429 ; Alias variable for select char @ 0 430 0033 send_byte__char__171select0 equ send_byte__char+0 431 0033 send_byte__char__171select0__byte equ send_byte__char+0 432 0000 send_byte__char__171select0__bit equ 0 433 07e 713 btfss send_byte__char__171select0__byte,send_byte__char__171select0__bit 434 07f 4a6 bcf serial_out__byte,serial_out__bit 435 080 613 btfsc send_byte__char__171select0__byte,send_byte__char__171select0__bit 436 081 5a6 bsf serial_out__byte,serial_out__bit 437 ; 2 cycles : 438 ; char := char >> 1 439 082 403 bcf c___byte,c___bit 440 083 333 rrf send_byte__char,f 441 ; call delay {{ }} 442 ; Switch from register bank 1 to register bank 0 443 084 4a4 bcf rp0___byte,rp0___bit 444 ; Register bank is now 0 445 085 997 call delay 446 ; call delay {{ }} 447 086 997 call delay 448 ; call delay {{ }} 449 087 997 call delay 450 ; 3 cycles at end of loop : 451 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 452 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 453 088 5a4 bsf rp0___byte,rp0___bit 454 ; Register bank is now 1 455 089 2f4 decfsz send_byte__count,f 456 08a a7e goto send_byte__169_loop 457 send_byte__169_done: 458 ; `count_down count 8 ...' end 459 ; Send the stop bit : 460 ; 1 cycle to close out previous loop : 461 ; nop 1 462 ; Delay 1 cycles 463 08b 000 nop 464 ; 1 cylce : 465 ; serial_out := 1 466 08c 5a6 bsf serial_out__byte,serial_out__bit 467 ; call delay {{ }} 468 ; Switch from register bank 1 to register bank 0 469 08d 4a4 bcf rp0___byte,rp0___bit 470 ; Register bank is now 0 471 08e 997 call delay 472 ; call delay {{ }} 473 08f 997 call delay 474 ; call delay {{ }} 475 090 997 call delay 476 ; 2 cycles for call / return : 477 ; 2 cycles for argument : 478 ; 1 + 2 + 2 = 5 479 ; nop extra_instructions_per_bit - 5 480 ; Delay 4 cycles 481 091 000 nop 482 092 000 nop 483 093 000 nop 484 094 000 nop 485 ; procedure send_byte end 486 ; Switch from register bank 0 to register bank 1 487 095 5a4 bsf rp0___byte,rp0___bit 488 ; Register bank is now 1 489 096 800 retlw 0 490 ; bank 0 491 ; Default register bank is now 0 492 493 ; procedure delay start 494 ; optimize 0 495 delay: 496 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 497 ; Procedure must be called with PCLATH set to code bank 0 498 000e delay__variables__base equ global__variables__bank0+7 499 000e delay__bytes__base equ delay__variables__base+0 500 0016 delay__bits__base equ delay__variables__base+8 501 0009 delay__total__bytes equ 9 502 0015 delay__264byte0 equ delay__bytes__base+7 503 0015 delay__197byte1 equ delay__bytes__base+7 504 0016 delay__239bit0 equ delay__bits__base+0 505 0016 delay__239bit0__byte equ delay__bits__base+0 506 0004 delay__239bit0__bit equ 4 507 0016 delay__243bit0 equ delay__bits__base+0 508 0016 delay__243bit0__byte equ delay__bits__base+0 509 0004 delay__243bit0__bit equ 4 510 ; arguments_none 511 ; uniform_delay delay_instructions 512 ; Uniform delay remaining = 131 Accumulated Delay = 0 513 ; Uniform delay remaining = 131 Accumulated Delay = 0 514 ; Delay 1 / 3 of a bit : 515 ; Uniform delay remaining = 131 Accumulated Delay = 0 516 ; Uniform delay remaining = 131 Accumulated Delay = 0 517 000e delay__changed equ delay__bytes__base+0 518 ; Uniform delay remaining = 131 Accumulated Delay = 0 519 000f delay__current equ delay__bytes__base+1 520 ; Uniform delay remaining = 131 Accumulated Delay = 0 521 0010 delay__previous equ delay__bytes__base+2 522 ; Uniform delay remaining = 131 Accumulated Delay = 0 523 0011 delay__not_current equ delay__bytes__base+3 524 ; Uniform delay remaining = 131 Accumulated Delay = 0 525 0012 delay__counter1 equ delay__bytes__base+4 526 ; Uniform delay remaining = 131 Accumulated Delay = 0 527 0013 delay__counter2 equ delay__bytes__base+5 528 ; Uniform delay remaining = 131 Accumulated Delay = 0 529 0014 delay__counter3 equ delay__bytes__base+6 530 ; Uniform delay remaining = 131 Accumulated Delay = 0 531 ; Uniform delay remaining = 131 Accumulated Delay = 0 532 ; Kick the dog : 533 ; Uniform delay remaining = 131 Accumulated Delay = 0 534 ; watch_dog_reset 535 097 004 clrwdt 536 ; Uniform delay remaining = 130 Accumulated Delay = 1 537 ; Uniform delay remaining = 130 Accumulated Delay = 1 538 ; We need to pulse OUTn low for 56 ms ; read INn ; and restore OUTn high 539 ; Uniform delay remaining = 130 Accumulated Delay = 1 540 ; for 3 ms . 1 / 3 of a bit time is 1 / < 3 * 2400 > = 138 us . 56 ms / 138 ms = 406 541 ; Uniform delay remaining = 130 Accumulated Delay = 1 542 ; ticks . 3 ms / 138 us = 7 . 2 ticks which is rounded up to 8 ticks . Round 543 ; Uniform delay remaining = 130 Accumulated Delay = 1 544 ; 406 up to 408 so it is divisible by 8 < 408 / 8 = 51 > . 545 ; Uniform delay remaining = 130 Accumulated Delay = 1 546 ; counter1 := counter1 - 1 547 098 0f2 decf delay__counter1,f 548 ; Uniform delay remaining = 129 Accumulated Delay = 2 549 ; if { z } start 550 ; expression=`{ z }' exp_delay=0 true_delay=32 false_delay=37 true_size=109 false_size=41 551 099 743 btfss z__byte,z__bit 552 09a b0d goto label220__0false 553 label220__0true: 554 ; if { z } body start 555 ; Uniform delay remaining = 129 Accumulated Delay = 0 556 ; counter1 := 8 557 09b c08 movlw 8 558 09c 032 movwf delay__counter1 559 ; Uniform delay remaining = 127 Accumulated Delay = 2 560 ; counter2 := counter2 + 1 561 09d 2b3 incf delay__counter2,f 562 ; Uniform delay remaining = 126 Accumulated Delay = 3 563 ; if { counter2 = 1 } start 564 09e 0d3 decf delay__counter2,w 565 ; expression=`{ counter2 = 1 }' exp_delay=1 true_delay=25 false_delay=21 true_size=43 false_size=56 566 09f 643 btfsc z___byte,z___bit 567 0a0 add goto label223__0true 568 label223__0false: 569 0a1 c33 movlw 51 570 0a2 093 subwf delay__counter2,w 571 ; expression=`{ counter2 = 51 }' exp_delay=2 true_delay=16 false_delay=12 true_size=30 false_size=18 572 0a3 643 btfsc z___byte,z___bit 573 0a4 abb goto label232__0true 574 label232__0false: 575 0a5 c34 movlw 52 576 0a6 093 subwf delay__counter2,w 577 ; expression=`{ counter2 = 52 }' exp_delay=2 true_delay=7 false_delay=0 true_size=7 false_size=0 578 0a7 643 btfsc z___byte,z___bit 579 0a8 ab0 goto label247__0true 580 label247__0false: 581 ; Delay 6 cycles 582 0a9 000 nop 583 0aa 000 nop 584 0ab 000 nop 585 0ac 000 nop 586 0ad 000 nop 587 0ae 000 nop 588 0af ab7 goto label247__0end 589 label247__0true: 590 ; else_if { counter2 = 52 } body start 591 ; Uniform delay remaining = 126 Accumulated Delay = 0 592 ; The 3 ms have elpased , next time we trigger again : 593 ; Uniform delay remaining = 126 Accumulated Delay = 0 594 ; inputs := inputs & 3 595 0b0 c03 movlw 3 596 0b1 167 andwf inputs,f 597 ; Uniform delay remaining = 124 Accumulated Delay = 2 598 ; if { ! {{ enable @ 0 }} } start 599 ; Alias variable for select enable @ 0 600 0008 enable__250select0 equ enable+0 601 0008 enable__250select0__byte equ enable+0 602 0000 enable__250select0__bit equ 0 603 ; expression=`{{ enable @ 0 }}' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 604 0b2 708 btfss enable__250select0__byte,enable__250select0__bit 605 ; if { ! {{ enable @ 0 }} } body start 606 ; Uniform delay remaining = 124 Accumulated Delay = 0 607 ; inputs @ 0 := 0 608 ; Select inputs @ 0 609 0007 inputs__251select0 equ inputs+0 610 0007 inputs__251select0__byte equ inputs+0 611 0000 inputs__251select0__bit equ 0 612 0b3 407 bcf inputs__251select0__byte,inputs__251select0__bit 613 ; Uniform delay remaining = 123 Accumulated Delay = 1 614 ; Uniform delay remaining = 123 Accumulated Delay = 1 615 ; if { ! {{ enable @ 0 }} } body end 616 ; if exp=` enable @ 0 ' true skip delay=2 617 ; Other expression=`{{ enable @ 0 }}' delay=2 618 ; if { ! {{ enable @ 0 }} } end 619 ; Uniform delay remaining = 122 Accumulated Delay = 4 620 ; if { ! {{ enable @ 1 }} } start 621 ; Alias variable for select enable @ 1 622 0008 enable__253select0 equ enable+0 623 0008 enable__253select0__byte equ enable+0 624 0001 enable__253select0__bit equ 1 625 ; expression=`{{ enable @ 1 }}' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 626 0b4 728 btfss enable__253select0__byte,enable__253select0__bit 627 ; if { ! {{ enable @ 1 }} } body start 628 ; Uniform delay remaining = 122 Accumulated Delay = 0 629 ; inputs @ 1 := 0 630 ; Select inputs @ 1 631 0007 inputs__254select0 equ inputs+0 632 0007 inputs__254select0__byte equ inputs+0 633 0001 inputs__254select0__bit equ 1 634 0b5 427 bcf inputs__254select0__byte,inputs__254select0__bit 635 ; Uniform delay remaining = 121 Accumulated Delay = 1 636 ; Uniform delay remaining = 121 Accumulated Delay = 1 637 ; if { ! {{ enable @ 1 }} } body end 638 ; if exp=` enable @ 1 ' true skip delay=2 639 ; Other expression=`{{ enable @ 1 }}' delay=2 640 ; if { ! {{ enable @ 1 }} } end 641 ; Uniform delay remaining = 120 Accumulated Delay = 6 642 ; counter2 := 0 643 0b6 073 clrf delay__counter2 644 ; Uniform delay remaining = 119 Accumulated Delay = 7 645 ; Uniform delay remaining = 119 Accumulated Delay = 7 646 ; else_if { counter2 = 52 } body end 647 ; if exp=` counter2 = 52 ' total delay=12 648 ; if exp=` counter2 = 52 ' generic 649 label247__0end: 650 ; Other expression=`{ counter2 = 52 }' delay=12 651 ; Delay 3 cycles 652 0b7 000 nop 653 0b8 000 nop 654 0b9 000 nop 655 0ba ad9 goto label232__0end 656 label232__0true: 657 ; else_if { counter2 = 51 } body start 658 ; Uniform delay remaining = 126 Accumulated Delay = 0 659 ; Approximately 56 ms have elpased ; 660 ; Uniform delay remaining = 126 Accumulated Delay = 0 661 ; Time to read data and reset any triggers : 662 ; Uniform delay remaining = 126 Accumulated Delay = 0 663 ; Note : the compiler is generating pretty awful code 664 ; Uniform delay remaining = 126 Accumulated Delay = 0 665 ; for th next couple of statements . It works , but it 666 ; Uniform delay remaining = 126 Accumulated Delay = 0 667 ; is not pretty . 668 ; Uniform delay remaining = 126 Accumulated Delay = 0 669 ; if { ! out0 } start 670 ; expression=`out0' exp_delay=0 true_delay=0 false_delay=5 true_size=0 false_size=8 671 0bb 706 btfss out0__byte,out0__bit 672 0bc ac2 goto label238__0false 673 label238__0true: 674 ; Delay 4 cycles 675 0bd 000 nop 676 0be 000 nop 677 0bf 000 nop 678 0c0 000 nop 679 0c1 aca goto label238__0end 680 label238__0false: 681 ; if { ! out0 } body start 682 ; Uniform delay remaining = 126 Accumulated Delay = 0 683 ; inputs @ 0 := ! in0 684 0c2 496 bcf delay__239bit0__byte,delay__239bit0__bit 685 0c3 726 btfss in0__byte,in0__bit 686 0c4 596 bsf delay__239bit0__byte,delay__239bit0__bit 687 ; Select variable inputs @ 0 688 0007 inputs__239select1 equ inputs+0 689 0007 inputs__239select1__byte equ inputs+0 690 0000 inputs__239select1__bit equ 0 691 0c5 796 btfss delay__239bit0__byte,delay__239bit0__bit 692 0c6 407 bcf inputs__239select1__byte,inputs__239select1__bit 693 0c7 696 btfsc delay__239bit0__byte,delay__239bit0__bit 694 0c8 507 bsf inputs__239select1__byte,inputs__239select1__bit 695 ; Uniform delay remaining = 122 Accumulated Delay = 4 696 ; out0 := 1 697 0c9 506 bsf out0__byte,out0__bit 698 ; Uniform delay remaining = 121 Accumulated Delay = 5 699 ; Uniform delay remaining = 121 Accumulated Delay = 5 700 ; if { ! out0 } body end 701 ; if exp=`out0' total delay=8 702 ; if exp=`out0' generic 703 label238__0end: 704 ; Other expression=`out0' delay=8 705 ; if { ! out0 } end 706 ; Uniform delay remaining = 118 Accumulated Delay = 8 707 ; if { ! out1 } start 708 ; expression=`out1' exp_delay=0 true_delay=0 false_delay=5 true_size=0 false_size=8 709 0ca 746 btfss out1__byte,out1__bit 710 0cb ad1 goto label242__0false 711 label242__0true: 712 ; Delay 4 cycles 713 0cc 000 nop 714 0cd 000 nop 715 0ce 000 nop 716 0cf 000 nop 717 0d0 ad9 goto label242__0end 718 label242__0false: 719 ; if { ! out1 } body start 720 ; Uniform delay remaining = 118 Accumulated Delay = 0 721 ; inputs @ 1 := ! in1 722 0d1 496 bcf delay__243bit0__byte,delay__243bit0__bit 723 0d2 766 btfss in1__byte,in1__bit 724 0d3 596 bsf delay__243bit0__byte,delay__243bit0__bit 725 ; Select variable inputs @ 1 726 0007 inputs__243select1 equ inputs+0 727 0007 inputs__243select1__byte equ inputs+0 728 0001 inputs__243select1__bit equ 1 729 0d4 796 btfss delay__243bit0__byte,delay__243bit0__bit 730 0d5 427 bcf inputs__243select1__byte,inputs__243select1__bit 731 0d6 696 btfsc delay__243bit0__byte,delay__243bit0__bit 732 0d7 527 bsf inputs__243select1__byte,inputs__243select1__bit 733 ; Uniform delay remaining = 114 Accumulated Delay = 4 734 ; out1 := 1 735 0d8 546 bsf out1__byte,out1__bit 736 ; Uniform delay remaining = 113 Accumulated Delay = 5 737 ; Uniform delay remaining = 113 Accumulated Delay = 5 738 ; if { ! out1 } body end 739 ; if exp=`out1' total delay=8 740 ; if exp=`out1' generic 741 label242__0end: 742 ; Other expression=`out1' delay=8 743 ; if { ! out1 } end 744 ; Uniform delay remaining = 110 Accumulated Delay = 16 745 ; Now wait an additional 3 ms before triggering again : 746 ; Uniform delay remaining = 110 Accumulated Delay = 16 747 ; Uniform delay remaining = 110 Accumulated Delay = 16 748 ; else_if { counter2 = 51 } body end 749 ; if exp=` counter2 = 51 ' total delay=21 750 ; if exp=` counter2 = 51 ' generic 751 label232__0end: 752 ; Other expression=`{ counter2 = 51 }' delay=21 753 ; Delay 3 cycles 754 0d9 000 nop 755 0da 000 nop 756 0db 000 nop 757 0dc b08 goto label223__0end 758 label223__0true: 759 ; if { counter2 = 1 } body start 760 ; Uniform delay remaining = 126 Accumulated Delay = 0 761 ; Trigger the appropriate enabled IROD ' s : 762 ; Uniform delay remaining = 126 Accumulated Delay = 0 763 ; counter3 := counter3 + 1 764 0dd 2b4 incf delay__counter3,f 765 ; Uniform delay remaining = 125 Accumulated Delay = 1 766 ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } start 767 ; Alias variable for select enable @ 0 768 0008 enable__226select7 equ enable+0 769 0008 enable__226select7__byte equ enable+0 770 0000 enable__226select7__bit equ 0 771 ; expression=`enable @ 0' exp_delay=0 true_delay=9 false_delay=5 true_size=13 false_size=1 772 0de 608 btfsc enable__226select7__byte,enable__226select7__bit 773 0df ae6 goto label226__8true 774 label226__8false: 775 ; Delay 5 cycles 776 0e0 000 nop 777 0e1 000 nop 778 0e2 000 nop 779 0e3 000 nop 780 0e4 000 nop 781 0e5 af3 goto and226__0false 782 label226__8true: 783 ; expression=`alternate' exp_delay=0 true_delay=5 false_delay=3 true_size=6 false_size=1 784 0e6 757 btfss alternate__byte,alternate__bit 785 0e7 aef goto label226__6false 786 label226__6true: 787 ; expression=`alternate' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 788 0e8 657 btfsc alternate__byte,alternate__bit 789 0e9 aec goto label226__5true 790 label226__5false: 791 ; Delay 1 cycles 792 0ea 000 nop 793 0eb aee goto and226__2false 794 label226__5true: 795 ; Alias variable for select counter3 @ 0 796 0014 delay__counter3__226select3 equ delay__counter3+0 797 0014 delay__counter3__226select3__byte equ delay__counter3+0 798 0000 delay__counter3__226select3__bit equ 0 799 ; expression=`counter3 @ 0' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 800 0ec 614 btfsc delay__counter3__226select3__byte,delay__counter3__226select3__bit 801 and226__2true: 802 or226__1true: 803 and226__0true: 804 ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } body start 805 ; Uniform delay remaining = 125 Accumulated Delay = 0 806 ; out0 := 0 807 0ed 406 bcf out0__byte,out0__bit 808 ; Uniform delay remaining = 124 Accumulated Delay = 1 809 ; Uniform delay remaining = 124 Accumulated Delay = 1 810 ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } body end 811 ; if exp=`counter3 @ 0' false skip delay=2 812 ; Other expression=`counter3 @ 0' delay=2 813 ; if exp=`alternate' total delay=5 814 ; if exp=`alternate' generic 815 label226__5end: 816 ; Other expression=`alternate' delay=5 817 and226__2false: 818 and226__2end: 819 0ee af3 goto label226__6end 820 label226__6false: 821 ; Delay 3 cycles 822 0ef 000 nop 823 0f0 000 nop 824 0f1 000 nop 825 0f2 aed goto or226__1true 826 ; if exp=`alternate' total delay=9 827 ; if exp=`alternate' generic 828 label226__6end: 829 ; Other expression=`alternate' delay=9 830 or226__1false: 831 or226__1end: 832 ; if exp=`enable @ 0' total delay=12 833 ; if exp=`enable @ 0' generic 834 label226__8end: 835 ; Other expression=`enable @ 0' delay=12 836 and226__0false: 837 and226__0end: 838 ; if { enable @ 0 && {{ ! alternate || alternate && counter3 @ 0 }} } end 839 ; Uniform delay remaining = 113 Accumulated Delay = 13 840 ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } start 841 ; Alias variable for select enable @ 1 842 0008 enable__229select7 equ enable+0 843 0008 enable__229select7__byte equ enable+0 844 0001 enable__229select7__bit equ 1 845 ; expression=`enable @ 1' exp_delay=0 true_delay=9 false_delay=5 true_size=13 false_size=1 846 0f3 628 btfsc enable__229select7__byte,enable__229select7__bit 847 0f4 afb goto label229__8true 848 label229__8false: 849 ; Delay 5 cycles 850 0f5 000 nop 851 0f6 000 nop 852 0f7 000 nop 853 0f8 000 nop 854 0f9 000 nop 855 0fa b08 goto and229__0false 856 label229__8true: 857 ; expression=`alternate' exp_delay=0 true_delay=5 false_delay=3 true_size=6 false_size=1 858 0fb 757 btfss alternate__byte,alternate__bit 859 0fc b04 goto label229__6false 860 label229__6true: 861 ; expression=`alternate' exp_delay=0 true_delay=2 false_delay=2 true_size=2 false_size=1 862 0fd 657 btfsc alternate__byte,alternate__bit 863 0fe b01 goto label229__5true 864 label229__5false: 865 ; Delay 1 cycles 866 0ff 000 nop 867 100 b03 goto and229__2false 868 label229__5true: 869 ; Alias variable for select counter3 @ 0 870 0014 delay__counter3__229select3 equ delay__counter3+0 871 0014 delay__counter3__229select3__byte equ delay__counter3+0 872 0000 delay__counter3__229select3__bit equ 0 873 ; expression=`{{ counter3 @ 0 }}' exp_delay=0 true_delay=0 false_delay=1 true_size=0 false_size=1 874 101 714 btfss delay__counter3__229select3__byte,delay__counter3__229select3__bit 875 and229__2true: 876 or229__1true: 877 and229__0true: 878 ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } body start 879 ; Uniform delay remaining = 113 Accumulated Delay = 0 880 ; out1 := 0 881 102 446 bcf out1__byte,out1__bit 882 ; Uniform delay remaining = 112 Accumulated Delay = 1 883 ; Uniform delay remaining = 112 Accumulated Delay = 1 884 ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } body end 885 ; if exp=` counter3 @ 0 ' true skip delay=2 886 ; Other expression=`{{ counter3 @ 0 }}' delay=2 887 ; if exp=`alternate' total delay=5 888 ; if exp=`alternate' generic 889 label229__5end: 890 ; Other expression=`alternate' delay=5 891 and229__2false: 892 and229__2end: 893 103 b08 goto label229__6end 894 label229__6false: 895 ; Delay 3 cycles 896 104 000 nop 897 105 000 nop 898 106 000 nop 899 107 b02 goto or229__1true 900 ; if exp=`alternate' total delay=9 901 ; if exp=`alternate' generic 902 label229__6end: 903 ; Other expression=`alternate' delay=9 904 or229__1false: 905 or229__1end: 906 ; if exp=`enable @ 1' total delay=12 907 ; if exp=`enable @ 1' generic 908 label229__8end: 909 ; Other expression=`enable @ 1' delay=12 910 and229__0false: 911 and229__0end: 912 ; if { enable @ 1 && {{ ! alternate || alternate && ! {{ counter3 @ 0 }} }} } end 913 ; Uniform delay remaining = 101 Accumulated Delay = 25 914 ; Uniform delay remaining = 101 Accumulated Delay = 25 915 ; if { counter2 = 1 } body end 916 ; if exp=` counter2 = 1 ' total delay=29 917 ; if exp=` counter2 = 1 ' generic 918 label223__0end: 919 ; Other expression=`{ counter2 = 1 }' delay=29 920 ; if { counter2 = 1 } end 921 ; Uniform delay remaining = 97 Accumulated Delay = 32 922 ; Uniform delay remaining = 97 Accumulated Delay = 32 923 ; if { z } body end 924 ; Delay 4 cycles 925 108 000 nop 926 109 000 nop 927 10a 000 nop 928 10b 000 nop 929 10c b36 goto label220__0end 930 label220__0false: 931 ; else body start 932 ; Uniform delay remaining = 129 Accumulated Delay = 0 933 ; Compute the interrupts : 934 ; Uniform delay remaining = 129 Accumulated Delay = 0 935 ; previous := current 936 10d 20f movf delay__current,w 937 10e 030 movwf delay__previous 938 ; Uniform delay remaining = 127 Accumulated Delay = 2 939 ; current := {{ inputs ^ complement }} & 3 940 10f 207 movf inputs,w 941 110 189 xorwf complement,w 942 111 e03 andlw 3 943 112 02f movwf delay__current 944 ; Uniform delay remaining = 123 Accumulated Delay = 6 945 ; not_current := current ^ 3 946 113 c03 movlw 3 947 114 18f xorwf delay__current,w 948 115 031 movwf delay__not_current 949 ; Uniform delay remaining = 120 Accumulated Delay = 9 950 ; changed := current ^ previous 951 116 20f movf delay__current,w 952 117 190 xorwf delay__previous,w 953 118 02e movwf delay__changed 954 ; Uniform delay remaining = 117 Accumulated Delay = 12 955 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } start 956 119 20c movf low,w 957 11a 151 andwf delay__not_current,w 958 11b 035 movwf delay__264byte0 959 11c 20b movf high,w 960 11d 14f andwf delay__current,w 961 11e 135 iorwf delay__264byte0,f 962 11f 20e movf delay__changed,w 963 120 14f andwf delay__current,w 964 121 14d andwf raising,w 965 122 135 iorwf delay__264byte0,f 966 123 20e movf delay__changed,w 967 124 150 andwf delay__previous,w 968 125 14a andwf falling,w 969 126 115 iorwf delay__264byte0,w 970 ; expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 }' exp_delay=14 true_delay=1 false_delay=0 true_size=1 false_size=0 971 127 743 btfss z___byte,z___bit 972 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } body start 973 ; Uniform delay remaining = 117 Accumulated Delay = 0 974 ; interrupt_pending := 1 975 128 537 bsf interrupt_pending__byte,interrupt_pending__bit 976 ; Uniform delay remaining = 116 Accumulated Delay = 1 977 ; Uniform delay remaining = 116 Accumulated Delay = 1 978 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } body end 979 ; if exp=` {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 ' false skip delay=16 980 ; Other expression=`{ {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 }' delay=16 981 ; if { {{ low & not_current }} | {{ high & current }} | {{ changed & current & raising }} | {{ changed & previous & falling }} != 0 } end 982 ; Uniform delay remaining = 101 Accumulated Delay = 28 983 ; Uniform delay remaining = 101 Accumulated Delay = 28 984 ; Send an interrupt if interrupts are enabled : 985 ; Uniform delay remaining = 101 Accumulated Delay = 28 986 ; if { interrupt_pending && interrupt_enable } start 987 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 988 129 637 btfsc interrupt_pending__byte,interrupt_pending__bit 989 12a b2e goto label269__2true 990 label269__2false: 991 ; Delay 2 cycles 992 12b 000 nop 993 12c 000 nop 994 12d b36 goto and269__0false 995 label269__2true: 996 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 997 12e 717 btfss interrupt_enable__byte,interrupt_enable__bit 998 12f b33 goto label269__1false 999 label269__1true: 1000 and269__0true: 1001 ; if { interrupt_pending && interrupt_enable } body start 1002 ; Uniform delay remaining = 101 Accumulated Delay = 0 1003 ; Shove serial out to low : 1004 ; Uniform delay remaining = 101 Accumulated Delay = 0 1005 ; serial_out := 0 1006 130 4a6 bcf serial_out__byte,serial_out__bit 1007 ; Uniform delay remaining = 100 Accumulated Delay = 1 1008 ; interrupt_enable := 0 1009 131 417 bcf interrupt_enable__byte,interrupt_enable__bit 1010 ; Uniform delay remaining = 99 Accumulated Delay = 2 1011 ; Uniform delay remaining = 99 Accumulated Delay = 2 1012 ; if { interrupt_pending && interrupt_enable } body end 1013 132 b36 goto label269__1end 1014 label269__1false: 1015 ; Delay 3 cycles 1016 133 000 nop 1017 134 000 nop 1018 135 000 nop 1019 ; if exp=`interrupt_enable' total delay=6 1020 ; if exp=`interrupt_enable' generic 1021 label269__1end: 1022 ; Other expression=`interrupt_enable' delay=6 1023 ; if exp=`interrupt_pending' total delay=9 1024 ; if exp=`interrupt_pending' generic 1025 label269__2end: 1026 ; Other expression=`interrupt_pending' delay=9 1027 and269__0false: 1028 and269__0end: 1029 ; if { interrupt_pending && interrupt_enable } end 1030 ; Uniform delay remaining = 92 Accumulated Delay = 37 1031 ; Uniform delay remaining = 92 Accumulated Delay = 37 1032 ; else body end 1033 ; if exp=`z' total delay=40 1034 ; if exp=`z' generic 1035 label220__0end: 1036 ; Other expression=`{ z }' delay=40 1037 ; if { z } end 1038 ; Uniform delay remaining = 89 Accumulated Delay = 42 1039 ; Uniform delay remaining = 89 Accumulated Delay = 42 1040 ; Soak up remaining 89 cycles 1041 ; Delay 89 cycles 1042 136 c1d movlw 29 1043 137 035 movwf delay__197byte1 1044 delay__197delay0: 1045 138 2f5 decfsz delay__197byte1,f 1046 139 b38 goto delay__197delay0 1047 13a 000 nop 1048 ; procedure delay end 1049 13b 800 retlw 0 1050 ; optimize 1 1051 ; comment {The main routine can span the 256 byte boundary at 0x300 :} 1052 ; origin 0x200 1053 org 512 1054 ; bank 1 1055 ; Default register bank is now 1 1056 1057 ; procedure main start 1058 switch__329block_start: 1059 200 1e2 addwf pcl___register,f 1060 201 a57 goto switch__329block330 1061 202 a5f goto switch__329block334 1062 203 a65 goto switch__329block338 1063 204 a74 goto switch__329block346 1064 205 a7e goto switch__329block350 1065 206 a88 goto switch__329block354 1066 207 a92 goto switch__329block358 1067 208 a92 goto switch__329block358 1068 switch__329block_end: 1069 ; switch_check 329 switch__329block_start switch__329block_end 1070 switch__326block_start: 1071 209 1e2 addwf pcl___register,f 1072 20a a54 goto switch__326block327 1073 20b a9d goto switch__326block364 1074 20c a9e goto switch__326block367 1075 20d a9e goto switch__326block367 1076 20e aa7 goto switch__326block372 1077 20f aa7 goto switch__326block372 1078 210 ab0 goto switch__326block377 1079 211 ab0 goto switch__326block377 1080 switch__326block_end: 1081 ; switch_check 326 switch__326block_start switch__326block_end 1082 switch__406block_start: 1083 212 1e2 addwf pcl___register,f 1084 213 ae3 goto switch__406block407 1085 214 ae3 goto switch__406block407 1086 215 ae3 goto switch__406block407 1087 216 ae3 goto switch__406block407 1088 217 af6 goto switch__406block412 1089 218 af6 goto switch__406block412 1090 219 b01 goto switch__406block416 1091 21a b01 goto switch__406block416 1092 switch__406block_end: 1093 ; switch_check 406 switch__406block_start switch__406block_end 1094 switch__424block_start: 1095 21b 1e2 addwf pcl___register,f 1096 21c b0f goto switch__424block425 1097 21d b12 goto switch__424block429 1098 21e b15 goto switch__424block433 1099 21f b1b goto switch__424block437 1100 220 b20 goto switch__424block441 1101 221 b32 goto switch__424block452 1102 222 b34 goto switch__424block456 1103 223 b3b goto switch__424block461 1104 switch__424block_end: 1105 ; switch_check 424 switch__424block_start switch__424block_end 1106 switch__389block_start: 1107 224 1e2 addwf pcl___register,f 1108 225 b3e goto switch__389end 1109 226 b3e goto switch__389end 1110 227 b3e goto switch__389end 1111 228 b3e goto switch__389end 1112 229 b3e goto switch__389end 1113 22a ac0 goto switch__389block390 1114 22b ae0 goto switch__389block404 1115 22c b0c goto switch__389block422 1116 switch__389block_end: 1117 ; switch_check 389 switch__389block_start switch__389block_end 1118 switch__323block_start: 1119 22d 1e2 addwf pcl___register,f 1120 22e a4e goto switch__323block324 1121 22f ab9 goto switch__323block384 1122 230 ab9 goto switch__323block384 1123 231 aba goto switch__323block387 1124 switch__323block_end: 1125 ; switch_check 323 switch__323block_start switch__323block_end 1126 main: 1127 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1128 ; Procedure must be called with PCLATH set to code bank 0 1129 0035 main__variables__base equ global__variables__bank1+5 1130 0035 main__bytes__base equ main__variables__base+0 1131 003a main__bits__base equ main__variables__base+5 1132 0005 main__total__bytes equ 5 1133 0039 main__392byte0 equ main__bytes__base+4 1134 0039 main__374byte0 equ main__bytes__base+4 1135 0039 main__369byte0 equ main__bytes__base+4 1136 0039 main__356byte0 equ main__bytes__base+4 1137 0039 main__352byte0 equ main__bytes__base+4 1138 0039 main__379byte0 equ main__bytes__base+4 1139 0039 main__348byte0 equ main__bytes__base+4 1140 0039 main__326byte0 equ main__bytes__base+4 1141 0039 main__389byte0 equ main__bytes__base+4 1142 0039 main__323byte0 equ main__bytes__base+4 1143 ; arguments_none 1144 0035 main__command equ main__bytes__base+0 1145 0036 main__glitch equ main__bytes__base+1 1146 0037 main__id_index equ main__bytes__base+2 1147 0038 main__result equ main__bytes__base+3 1148 ; Let ROOT be http : / / web . gramlich . com / projects / robobricks 1149 ; For BIROD2 specific commands see : 1150 ; ROOT / birod2 / rev_a / index . html 1151 ; For shared commands see : 1152 ; ROOT / specifications . html # Software_Protocol 1153 ; For shared interrupt commands see : 1154 ; ROOT / specifications . html # Interrupts 1155 ; Initialize output pins : 1156 ; serial_out := 1 1157 232 5a6 bsf serial_out__byte,serial_out__bit 1158 ; out0 := 1 1159 233 506 bsf out0__byte,out0__bit 1160 ; out1 := 1 1161 234 546 bsf out1__byte,out1__bit 1162 ; Initialize everything else : 1163 ; interrupt_enable := 0 1164 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1165 235 4a4 bcf rp0___byte,rp0___bit 1166 ; Register bank is now 0 1167 236 417 bcf interrupt_enable__byte,interrupt_enable__bit 1168 ; interrupt_pending := 0 1169 237 437 bcf interrupt_pending__byte,interrupt_pending__bit 1170 ; alternate := 0 1171 238 457 bcf alternate__byte,alternate__bit 1172 ; enable := 3 1173 239 c03 movlw 3 1174 23a 028 movwf enable 1175 ; complement := 0 1176 23b 069 clrf complement 1177 ; falling := 0 1178 23c 06a clrf falling 1179 ; high := 0 1180 23d 06b clrf high 1181 ; low := 0 1182 23e 06c clrf low 1183 ; raising := 0 1184 23f 06d clrf raising 1185 ; glitch := 0 1186 ; Switch from register bank 0 to register bank 1 (which contains main__glitch) 1187 240 5a4 bsf rp0___byte,rp0___bit 1188 ; Register bank is now 1 1189 241 076 clrf main__glitch 1190 ; id_index := 0 1191 242 077 clrf main__id_index 1192 ; Infinite command loop : 1193 ; loop_forever ... start 1194 main__318loop__forever: 1195 ; Wait for command : 1196 ; command := get_byte {{ }} 1197 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1198 243 4a3 bcf pa0___byte,pa0___bit 1199 244 93d call get_byte 1200 245 210 movf get_byte__0return__byte,w 1201 246 035 movwf main__command 1202 ; Dispatch on command : 1203 ; switch { command >> 6 } 1204 247 395 swapf main__command,w 1205 248 039 movwf main__323byte0 1206 249 339 rrf main__323byte0,f 1207 24a 319 rrf main__323byte0,w 1208 24b e03 andlw 3 1209 ; case 0 1210 ; case 1 2 1211 ; case 3 1212 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1213 24c 5a3 bsf pa0___byte,pa0___bit 1214 24d a2d goto switch__323block_start 1215 switch__323block324: 1216 ; Command = 00 xx xxxx : 1217 ; switch { command >> 3 } 1218 24e 315 rrf main__command,w 1219 24f 039 movwf main__326byte0 1220 250 339 rrf main__326byte0,f 1221 251 319 rrf main__326byte0,w 1222 252 e1f andlw 31 1223 ; case 0 1224 ; case 1 1225 ; case 2 3 1226 ; case 4 5 1227 ; case 6 7 1228 253 a09 goto switch__326block_start 1229 switch__326block327: 1230 ; Command = 0000 0 xxx : 1231 ; switch { command & 7 } 1232 254 c07 movlw 7 1233 255 155 andwf main__command,w 1234 ; case 0 1235 ; case 1 1236 ; case 2 1237 ; case 3 1238 ; case 4 1239 ; case 5 1240 ; case 6 7 1241 256 a00 goto switch__329block_start 1242 switch__329block330: 1243 ; Read Inputs < Command = 0000 0000 > : 1244 ; call send_byte {{ {{ inputs ^ complement }} & 0xf }} 1245 257 207 movf inputs,w 1246 258 189 xorwf complement,w 1247 259 e0f andlw 15 1248 25a 033 movwf send_byte__char 1249 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1250 25b 4a3 bcf pa0___byte,pa0___bit 1251 25c 96a call send_byte 1252 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1253 25d 5a3 bsf pa0___byte,pa0___bit 1254 25e a9c goto switch__329end 1255 switch__329block334: 1256 ; Read Raw < Command = 0000 0001 > : 1257 ; call send_byte {{ inputs }} 1258 25f 207 movf inputs,w 1259 260 033 movwf send_byte__char 1260 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1261 261 4a3 bcf pa0___byte,pa0___bit 1262 262 96a call send_byte 1263 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1264 263 5a3 bsf pa0___byte,pa0___bit 1265 264 a9c goto switch__329end 1266 switch__329block338: 1267 ; Read Alternate < Command = 0000 0010 > : 1268 ; if { alternate } start 1269 ; expression=`{ alternate }' exp_delay=0 true_delay=0 false_delay=-1 true_size=2 false_size=1 1270 ; Switch from register bank 1 to register bank 0 (which contains alternate__byte) 1271 265 4a4 bcf rp0___byte,rp0___bit 1272 ; Register bank is now 0 1273 266 443 bcf z___byte,z___bit 1274 267 657 btfsc alternate__byte,alternate__bit 1275 268 543 bsf z___byte,z___bit 1276 ; Switch from register bank 0 to register bank 1 1277 269 5a4 bsf rp0___byte,rp0___bit 1278 ; Register bank is now 1 1279 26a 643 btfsc z___byte,z___bit 1280 26b a6e goto label340__0true 1281 label340__0false: 1282 ; else body start 1283 ; call send_byte {{ 0 }} 1284 26c 073 clrf send_byte__char 1285 ; 1 instructions found for sharing 1286 26d a70 goto label340__0end 1287 label340__0true: 1288 ; if { alternate } body start 1289 ; call send_byte {{ 1 }} 1290 26e c01 movlw 1 1291 26f 033 movwf send_byte__char 1292 ; 1 instructions found for sharing 1293 ; if exp=`alternate' generic 1294 label340__0end: 1295 ; Other expression=`{ alternate }' delay=-1 1296 ; 1 shared instructions follow 1297 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1298 270 4a3 bcf pa0___byte,pa0___bit 1299 271 96a call send_byte 1300 ; if { alternate } end 1301 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1302 272 5a3 bsf pa0___byte,pa0___bit 1303 273 a9c goto switch__329end 1304 switch__329block346: 1305 ; Read Enable Complement Masks < Command = 0000 0011 > : 1306 ; call send_byte {{ {{ enable << 2 }} | complement }} 1307 274 348 rlf enable,w 1308 275 039 movwf main__348byte0 1309 276 359 rlf main__348byte0,w 1310 277 efc andlw 252 1311 278 109 iorwf complement,w 1312 279 033 movwf send_byte__char 1313 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1314 27a 4a3 bcf pa0___byte,pa0___bit 1315 27b 96a call send_byte 1316 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1317 27c 5a3 bsf pa0___byte,pa0___bit 1318 27d a9c goto switch__329end 1319 switch__329block350: 1320 ; Read High Low Masks < Command = 0000 0100 > : 1321 ; call send_byte {{ {{ high << 2 }} | low }} 1322 27e 34b rlf high,w 1323 27f 039 movwf main__352byte0 1324 280 359 rlf main__352byte0,w 1325 281 efc andlw 252 1326 282 10c iorwf low,w 1327 283 033 movwf send_byte__char 1328 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1329 284 4a3 bcf pa0___byte,pa0___bit 1330 285 96a call send_byte 1331 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1332 286 5a3 bsf pa0___byte,pa0___bit 1333 287 a9c goto switch__329end 1334 switch__329block354: 1335 ; Read Raising Falling Masks < Command = 0000 0101 > : 1336 ; call send_byte {{ {{ raising << 2 }} | falling }} 1337 288 34d rlf raising,w 1338 289 039 movwf main__356byte0 1339 28a 359 rlf main__356byte0,w 1340 28b efc andlw 252 1341 28c 10a iorwf falling,w 1342 28d 033 movwf send_byte__char 1343 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1344 28e 4a3 bcf pa0___byte,pa0___bit 1345 28f 96a call send_byte 1346 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1347 290 5a3 bsf pa0___byte,pa0___bit 1348 291 a9c goto switch__329end 1349 switch__329block358: 1350 ; Set alternate bit < Command = 0000 011 a > : 1351 ; alternate := command @ 0 1352 ; Alias variable for select command @ 0 1353 0035 main__command__360select0 equ main__command+0 1354 0035 main__command__360select0__byte equ main__command+0 1355 0000 main__command__360select0__bit equ 0 1356 ; Switch from register bank 1 to register bank 0 (which contains alternate__byte) 1357 292 4a4 bcf rp0___byte,rp0___bit 1358 ; Register bank is now 0 1359 293 457 bcf alternate__byte,alternate__bit 1360 ; Switch from register bank 0 to register bank 1 (which contains main__command__360select0__byte) 1361 294 5a4 bsf rp0___byte,rp0___bit 1362 ; Register bank is now 1 1363 295 443 bcf z___byte,z___bit 1364 296 615 btfsc main__command__360select0__byte,main__command__360select0__bit 1365 297 543 bsf z___byte,z___bit 1366 ; Switch from register bank 1 to register bank 0 (which contains alternate__byte) 1367 298 4a4 bcf rp0___byte,rp0___bit 1368 ; Register bank is now 0 1369 299 643 btfsc z___byte,z___bit 1370 29a 557 bsf alternate__byte,alternate__bit 1371 ; Switch from register bank 0 to register bank 1 1372 29b 5a4 bsf rp0___byte,rp0___bit 1373 ; Register bank is now 1 1374 switch__329end: 1375 29c ab8 goto switch__326end 1376 switch__326block364: 1377 ; Undefinded command ; do nothing : 1378 29d ab8 goto switch__326end 1379 switch__326block367: 1380 ; Set Enable Complement Masks < Command = 0001 eecc > : 1381 ; enable := {{ command >> 2 }} & 3 1382 29e 315 rrf main__command,w 1383 29f 039 movwf main__369byte0 1384 2a0 319 rrf main__369byte0,w 1385 2a1 e03 andlw 3 1386 2a2 028 movwf enable 1387 ; complement := command & 3 1388 2a3 c03 movlw 3 1389 2a4 155 andwf main__command,w 1390 2a5 029 movwf complement 1391 2a6 ab8 goto switch__326end 1392 switch__326block372: 1393 ; Set High Low Masks < Command = 0010 hhll > : 1394 ; high := {{ command >> 2 }} & 3 1395 2a7 315 rrf main__command,w 1396 2a8 039 movwf main__374byte0 1397 2a9 319 rrf main__374byte0,w 1398 2aa e03 andlw 3 1399 2ab 02b movwf high 1400 ; low := command & 3 1401 2ac c03 movlw 3 1402 2ad 155 andwf main__command,w 1403 2ae 02c movwf low 1404 2af ab8 goto switch__326end 1405 switch__326block377: 1406 ; Set Raising Falling Mask < Command = 0011 rrff > : 1407 ; raising := {{ command >> 2 }} & 3 1408 2b0 315 rrf main__command,w 1409 2b1 039 movwf main__379byte0 1410 2b2 319 rrf main__379byte0,w 1411 2b3 e03 andlw 3 1412 2b4 02d movwf raising 1413 ; falling := command & 3 1414 2b5 c03 movlw 3 1415 2b6 155 andwf main__command,w 1416 2b7 02a movwf falling 1417 switch__326end: 1418 2b8 b3e goto switch__323end 1419 switch__323block384: 1420 ; Do nothing < Command = 01 xx xxxx or 10 xx xxxx > : 1421 2b9 b3e goto switch__323end 1422 switch__323block387: 1423 ; Command = 11 xx xxxx : 1424 ; switch { {{ command >> 3 }} & 7 } 1425 2ba 315 rrf main__command,w 1426 2bb 039 movwf main__389byte0 1427 2bc 339 rrf main__389byte0,f 1428 2bd 319 rrf main__389byte0,w 1429 2be e07 andlw 7 1430 ; case 5 1431 ; case 6 1432 ; case 7 1433 2bf a24 goto switch__389block_start 1434 switch__389block390: 1435 ; Command = 1110 1 xxx : 1436 ; if { {{ command & 7 }} = 7 } start 1437 2c0 c07 movlw 7 1438 2c1 155 andwf main__command,w 1439 2c2 039 movwf main__392byte0 1440 2c3 c07 movlw 7 1441 2c4 099 subwf main__392byte0,w 1442 ; expression=`{ {{ command & 7 }} = 7 }' exp_delay=5 true_delay=-1 false_delay=0 true_size=12 false_size=0 1443 2c5 743 btfss z___byte,z___bit 1444 2c6 adf goto label392__1end 1445 ; if { {{ command & 7 }} = 7 } body start 1446 ; Return Interrupt Bits < Command = 1110 1111 > : 1447 ; result := 0 1448 2c7 078 clrf main__result 1449 ; if { interrupt_enable } start 1450 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1451 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1452 2c8 4a4 bcf rp0___byte,rp0___bit 1453 ; Register bank is now 0 1454 2c9 443 bcf z___byte,z___bit 1455 2ca 617 btfsc interrupt_enable__byte,interrupt_enable__bit 1456 2cb 543 bsf z___byte,z___bit 1457 ; Switch from register bank 0 to register bank 1 1458 2cc 5a4 bsf rp0___byte,rp0___bit 1459 ; Register bank is now 1 1460 2cd 743 btfss z___byte,z___bit 1461 2ce ad1 goto label395__0end 1462 ; if { interrupt_enable } body start 1463 ; result := result | 2 1464 2cf c02 movlw 2 1465 2d0 138 iorwf main__result,f 1466 ; if { interrupt_enable } body end 1467 label395__0end: 1468 ; if exp=`interrupt_enable' empty false 1469 ; Other expression=`{ interrupt_enable }' delay=-1 1470 ; if { interrupt_enable } end 1471 ; if { interrupt_pending } start 1472 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1473 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1474 2d1 4a4 bcf rp0___byte,rp0___bit 1475 ; Register bank is now 0 1476 2d2 443 bcf z___byte,z___bit 1477 2d3 637 btfsc interrupt_pending__byte,interrupt_pending__bit 1478 2d4 543 bsf z___byte,z___bit 1479 ; Switch from register bank 0 to register bank 1 1480 2d5 5a4 bsf rp0___byte,rp0___bit 1481 ; Register bank is now 1 1482 2d6 743 btfss z___byte,z___bit 1483 2d7 ada goto label398__0end 1484 ; if { interrupt_pending } body start 1485 ; result := result | 1 1486 2d8 c01 movlw 1 1487 2d9 138 iorwf main__result,f 1488 ; if { interrupt_pending } body end 1489 label398__0end: 1490 ; if exp=`interrupt_pending' empty false 1491 ; Other expression=`{ interrupt_pending }' delay=-1 1492 ; if { interrupt_pending } end 1493 ; call send_byte {{ result }} 1494 2da 218 movf main__result,w 1495 2db 033 movwf send_byte__char 1496 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1497 2dc 4a3 bcf pa0___byte,pa0___bit 1498 2dd 96a call send_byte 1499 ; if { {{ command & 7 }} = 7 } body end 1500 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1501 2de 5a3 bsf pa0___byte,pa0___bit 1502 label392__1end: 1503 ; if exp=` {{ command & 7 }} = 7 ' empty false 1504 ; Other expression=`{ {{ command & 7 }} = 7 }' delay=-1 1505 ; if { {{ command & 7 }} = 7 } end 1506 2df b3e goto switch__389end 1507 switch__389block404: 1508 ; Shared Interrupt commands < Command = 1111 0 xxx > : 1509 ; switch { command & 7 } 1510 2e0 c07 movlw 7 1511 2e1 155 andwf main__command,w 1512 ; case 0 1 2 3 1513 ; case 4 5 1514 ; case 6 7 1515 2e2 a12 goto switch__406block_start 1516 switch__406block407: 1517 ; Set interrupt enable and pending < Command = 1111 00 ep > : 1518 ; interrupt_enable := command @ 1 1519 ; Alias variable for select command @ 1 1520 0035 main__command__409select0 equ main__command+0 1521 0035 main__command__409select0__byte equ main__command+0 1522 0001 main__command__409select0__bit equ 1 1523 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1524 2e3 4a4 bcf rp0___byte,rp0___bit 1525 ; Register bank is now 0 1526 2e4 417 bcf interrupt_enable__byte,interrupt_enable__bit 1527 ; Switch from register bank 0 to register bank 1 (which contains main__command__409select0__byte) 1528 2e5 5a4 bsf rp0___byte,rp0___bit 1529 ; Register bank is now 1 1530 2e6 443 bcf z___byte,z___bit 1531 2e7 635 btfsc main__command__409select0__byte,main__command__409select0__bit 1532 2e8 543 bsf z___byte,z___bit 1533 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1534 2e9 4a4 bcf rp0___byte,rp0___bit 1535 ; Register bank is now 0 1536 2ea 643 btfsc z___byte,z___bit 1537 2eb 517 bsf interrupt_enable__byte,interrupt_enable__bit 1538 ; interrupt_pending := command @ 0 1539 ; Alias variable for select command @ 0 1540 0035 main__command__410select0 equ main__command+0 1541 0035 main__command__410select0__byte equ main__command+0 1542 0000 main__command__410select0__bit equ 0 1543 2ec 437 bcf interrupt_pending__byte,interrupt_pending__bit 1544 ; Switch from register bank 0 to register bank 1 (which contains main__command__410select0__byte) 1545 2ed 5a4 bsf rp0___byte,rp0___bit 1546 ; Register bank is now 1 1547 2ee 443 bcf z___byte,z___bit 1548 2ef 615 btfsc main__command__410select0__byte,main__command__410select0__bit 1549 2f0 543 bsf z___byte,z___bit 1550 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1551 2f1 4a4 bcf rp0___byte,rp0___bit 1552 ; Register bank is now 0 1553 2f2 643 btfsc z___byte,z___bit 1554 2f3 537 bsf interrupt_pending__byte,interrupt_pending__bit 1555 ; Switch from register bank 0 to register bank 1 1556 2f4 5a4 bsf rp0___byte,rp0___bit 1557 ; Register bank is now 1 1558 2f5 b0b goto switch__406end 1559 switch__406block412: 1560 ; Set Interrupt pending bit only < Command = 1111 010 p > : 1561 ; interrupt_pending := command @ 0 1562 ; Alias variable for select command @ 0 1563 0035 main__command__414select0 equ main__command+0 1564 0035 main__command__414select0__byte equ main__command+0 1565 0000 main__command__414select0__bit equ 0 1566 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1567 2f6 4a4 bcf rp0___byte,rp0___bit 1568 ; Register bank is now 0 1569 2f7 437 bcf interrupt_pending__byte,interrupt_pending__bit 1570 ; Switch from register bank 0 to register bank 1 (which contains main__command__414select0__byte) 1571 2f8 5a4 bsf rp0___byte,rp0___bit 1572 ; Register bank is now 1 1573 2f9 443 bcf z___byte,z___bit 1574 2fa 615 btfsc main__command__414select0__byte,main__command__414select0__bit 1575 2fb 543 bsf z___byte,z___bit 1576 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 1577 2fc 4a4 bcf rp0___byte,rp0___bit 1578 ; Register bank is now 0 1579 2fd 643 btfsc z___byte,z___bit 1580 2fe 537 bsf interrupt_pending__byte,interrupt_pending__bit 1581 ; Switch from register bank 0 to register bank 1 1582 2ff 5a4 bsf rp0___byte,rp0___bit 1583 ; Register bank is now 1 1584 300 b0b goto switch__406end 1585 switch__406block416: 1586 ; Set Interrupt pending bit only < Command = 1111 011 e > : 1587 ; interrupt_enable := command @ 0 1588 ; Alias variable for select command @ 0 1589 0035 main__command__418select0 equ main__command+0 1590 0035 main__command__418select0__byte equ main__command+0 1591 0000 main__command__418select0__bit equ 0 1592 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1593 301 4a4 bcf rp0___byte,rp0___bit 1594 ; Register bank is now 0 1595 302 417 bcf interrupt_enable__byte,interrupt_enable__bit 1596 ; Switch from register bank 0 to register bank 1 (which contains main__command__418select0__byte) 1597 303 5a4 bsf rp0___byte,rp0___bit 1598 ; Register bank is now 1 1599 304 443 bcf z___byte,z___bit 1600 305 615 btfsc main__command__418select0__byte,main__command__418select0__bit 1601 306 543 bsf z___byte,z___bit 1602 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 1603 307 4a4 bcf rp0___byte,rp0___bit 1604 ; Register bank is now 0 1605 308 643 btfsc z___byte,z___bit 1606 309 517 bsf interrupt_enable__byte,interrupt_enable__bit 1607 ; Switch from register bank 0 to register bank 1 1608 30a 5a4 bsf rp0___byte,rp0___bit 1609 ; Register bank is now 1 1610 switch__406end: 1611 30b b3e goto switch__389end 1612 switch__389block422: 1613 ; Shared commands . 1614 ; switch { command & 7 } 1615 30c c07 movlw 7 1616 30d 155 andwf main__command,w 1617 ; case 0 1618 ; case 1 1619 ; case 2 1620 ; case 3 1621 ; case 4 1622 ; case 5 1623 ; case 6 1624 ; case 7 1625 30e a1b goto switch__424block_start 1626 switch__424block425: 1627 ; Clock Decrement < Command = 1111 1000 > : 1628 ; osccal := osccal - osccal_unit 1629 30f cfc movlw 252 1630 310 1e5 addwf osccal,f 1631 311 b3e goto switch__424end 1632 switch__424block429: 1633 ; Clock Increment < Command = 1111 1001 > : 1634 ; osccal := osccal + osccal_unit 1635 312 c04 movlw 4 1636 313 1e5 addwf osccal,f 1637 314 b3e goto switch__424end 1638 switch__424block433: 1639 ; Clock Read < Command = 1111 1010 > : 1640 ; call send_byte {{ osccal }} 1641 315 205 movf osccal,w 1642 316 033 movwf send_byte__char 1643 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1644 317 4a3 bcf pa0___byte,pa0___bit 1645 318 96a call send_byte 1646 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1647 319 5a3 bsf pa0___byte,pa0___bit 1648 31a b3e goto switch__424end 1649 switch__424block437: 1650 ; Clock Pulse < Command = 1111 1011 > : 1651 ; call send_byte {{ 0 }} 1652 31b 073 clrf send_byte__char 1653 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1654 31c 4a3 bcf pa0___byte,pa0___bit 1655 31d 96a call send_byte 1656 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1657 31e 5a3 bsf pa0___byte,pa0___bit 1658 31f b3e goto switch__424end 1659 switch__424block441: 1660 ; ID Next < Command = 1111 1100 > : 1661 ; if { id_index >= id . size } start 1662 320 c30 movlw 48 1663 321 097 subwf main__id_index,w 1664 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1665 322 603 btfsc c___byte,c___bit 1666 ; if { id_index >= id . size } body start 1667 ; id_index := 0 1668 323 077 clrf main__id_index 1669 ; if { id_index >= id . size } body end 1670 ; if exp=` id_index >= id . size ' false skip delay=4 1671 ; Other expression=`{ id_index >= id . size }' delay=4 1672 ; if { id_index >= id . size } end 1673 ; call send_byte {{ id ~~ {{ id_index }} }} 1674 324 297 incf main__id_index,w 1675 ; Switch from register bank 1 to register bank 0 1676 325 4a4 bcf rp0___byte,rp0___bit 1677 ; Register bank is now 0 1678 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1679 326 4a3 bcf pa0___byte,pa0___bit 1680 327 90b call id 1681 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 1682 328 5a4 bsf rp0___byte,rp0___bit 1683 ; Register bank is now 1 1684 329 033 movwf send_byte__char 1685 32a 96a call send_byte 1686 ; id_index := id_index + 1 1687 32b 2b7 incf main__id_index,f 1688 ; if { id_index >= id . size } start 1689 32c c30 movlw 48 1690 32d 097 subwf main__id_index,w 1691 ; expression=`{ id_index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 1692 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) 1693 32e 5a3 bsf pa0___byte,pa0___bit 1694 32f 603 btfsc c___byte,c___bit 1695 ; if { id_index >= id . size } body start 1696 ; id_index := 0 1697 330 077 clrf main__id_index 1698 ; if { id_index >= id . size } body end 1699 ; if exp=` id_index >= id . size ' false skip delay=4 1700 ; Other expression=`{ id_index >= id . size }' delay=4 1701 ; if { id_index >= id . size } end 1702 331 b3e goto switch__424end 1703 switch__424block452: 1704 ; ID Reset < Command = 1111 1101 > : 1705 ; id_index := 0 1706 332 077 clrf main__id_index 1707 333 b3e goto switch__424end 1708 switch__424block456: 1709 ; Glitch Read < Command = 1111 1110 > : 1710 ; call send_byte {{ glitch }} 1711 334 216 movf main__glitch,w 1712 335 033 movwf send_byte__char 1713 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1714 336 4a3 bcf pa0___byte,pa0___bit 1715 337 96a call send_byte 1716 ; glitch := 0 1717 338 076 clrf main__glitch 1718 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1719 339 5a3 bsf pa0___byte,pa0___bit 1720 33a b3e goto switch__424end 1721 switch__424block461: 1722 ; Glitch < Command = 1111 1111 > : 1723 ; if { glitch != 0xff } start 1724 33b 296 incf main__glitch,w 1725 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1726 33c 743 btfss z___byte,z___bit 1727 ; if { glitch != 0xff } body start 1728 ; glitch := glitch + 1 1729 33d 2b6 incf main__glitch,f 1730 ; if { glitch != 0xff } body end 1731 ; if exp=` glitch != 0xff ' false skip delay=3 1732 ; Other expression=`{ glitch != 0xff }' delay=3 1733 ; if { glitch != 0xff } end 1734 switch__424end: 1735 switch__389end: 1736 switch__323end: 1737 33e a43 goto main__318loop__forever 1738 ; loop_forever ... end 1739 ; procedure main end 1740 1741 ; Register bank 0 used 16 bytes of 25 available bytes 1742 ; Register bank 1 used 10 bytes of 16 available bytes 1743 1744 end