1 radix dec 2 0008 global__variables__bank0 equ 8 3 0030 global__variables__bank1 equ 48 4 0050 global__variables__bank2 equ 80 5 0070 global__variables__bank3 equ 112 6 001e global__bit__variables__bank0 equ 30 7 003e global__bit__variables__bank1 equ 62 8 0050 global__bit__variables__bank2 equ 80 9 0070 global__bit__variables__bank3 equ 112 10 0000 indf___register equ 0 11 0002 pcl___register equ 2 12 0003 c___byte equ 3 13 0000 c___bit equ 0 14 0003 z___byte equ 3 15 0002 z___bit equ 2 16 ; On 12-bit PIC's, RP0 is actually bit 5 in FSR (=4) 17 0004 rp0___byte equ 4 18 0005 rp0___bit equ 5 19 ; On 12-bit PIC's, RP1 is actually bit 6 in FSR (=4) 20 0004 rp1___byte equ 4 21 0006 rp1___bit equ 6 22 ; On 12-bit PIC's, PA0 is actually bit 5 in STATUS (=3) 23 0003 pa0___byte equ 3 24 0005 pa0___bit equ 5 25 0004 fsr___register equ 4 26 org 0 27 start: 28 ; Use oscillator calibration value already in register W 29 000 025 movwf 5 30 ; Initialize TRIS registers 31 001 cfb movlw 251 32 002 006 tris 6 33 003 cff movlw 255 34 004 007 tris 7 35 ; Switch from register bank 0 to register bank 1 36 005 5a4 bsf rp0___byte,rp0___bit 37 ; Register bank is now 1 38 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 39 006 5a3 bsf pa0___byte,pa0___bit 40 007 a58 goto main 41 ; comment ############################################################################# 42 ; comment {} 43 ; comment {Copyright < c > 2000 - 2001 by Wayne C . Gramlich and Bill Benson} 44 ; comment {All rights reserved .} 45 ; comment {} 46 ; comment {Permission to use , copy , modify , distribute , and sell this software} 47 ; comment {for any purpose is hereby granted without fee provided that the above} 48 ; comment {copyright notice and this permission are retained . The author makes} 49 ; comment {no representations about the suitability of this software for any purpose .} 50 ; comment {It is provided { as is } without express or implied warranty .} 51 ; comment {} 52 ; comment {This is the code that implements the Out10 RoboBrick . Basically} 53 ; comment {it just waits for commands that come in at 2400 baud and responds} 54 ; comment {to them . See} 55 ; comment {} 56 ; comment {http : / / web . gramlich . net / projects / robobricks / out10 / index . html} 57 ; comment {} 58 ; comment {for more details .} 59 ; comment {} 60 ; comment ############################################################################# 61 ; processor pic16c505 cp = off wdte = on mclre = off fosc = intrc_no_clock 62 ; 4052=0xfd4 4095=0xfff 63 __config 4052 64 0fff configuration___address equ 4095 65 ; comment {Define processor constants :} 66 ; constant clock_rate 4000000 67 3d0900 clock_rate equ 4000000 68 ; constant clocks_per_instruction 4 69 0004 clocks_per_instruction equ 4 70 ; constant instruction_rate clock_rate / clocks_per_instruction 71 f4240 instruction_rate equ 1000000 72 ; comment {Define serial communication control constants :} 73 ; constant baud_rate 2400 74 0960 baud_rate equ 2400 75 ; constant instructions_per_bit instruction_rate / baud_rate 76 01a0 instructions_per_bit equ 416 77 ; constant delays_per_bit 3 78 0003 delays_per_bit equ 3 79 ; constant instructions_per_delay instructions_per_bit / delays_per_bit 80 008a instructions_per_delay equ 138 81 ; constant extra_instructions_per_bit 9 82 0009 extra_instructions_per_bit equ 9 83 ; constant extra_instructions_per_delay extra_instructions_per_bit / delays_per_bit 84 0003 extra_instructions_per_delay equ 3 85 ; constant delay_instructions instructions_per_delay - extra_instructions_per_delay 86 0087 delay_instructions equ 135 87 ; comment {Register definitions :} 88 ; comment {Status register :} 89 0003 status equ 3 90 ; bind c status @ 0 91 0003 c equ status+0 92 0003 c__byte equ status+0 93 0000 c__bit equ 0 94 ; bind z status @ 2 95 0003 z equ status+0 96 0003 z__byte equ status+0 97 0002 z__bit equ 2 98 ; comment {OSCCAL register :} 99 0005 osccal equ 5 100 ; constant osccal_lsb 4 101 0004 osccal_lsb equ 4 102 ; comment {Define bit offsets :} 103 ; constant io0_bit 0 104 0000 io0_bit equ 0 105 ; constant io1_bit 1 106 0001 io1_bit equ 1 107 ; constant io2_bit 2 108 0002 io2_bit equ 2 109 ; constant io3_bit 3 110 0003 io3_bit equ 3 111 ; constant io4_bit 4 112 0004 io4_bit equ 4 113 ; constant io5_bit 5 114 0005 io5_bit equ 5 115 ; constant io6_bit 4 116 0004 io6_bit equ 4 117 ; constant io7_bit 5 118 0005 io7_bit equ 5 119 ; constant io8_bit 0 120 0000 io8_bit equ 0 121 ; constant io9_bit 1 122 0001 io9_bit equ 1 123 ; constant serial_out_bit 2 124 0002 serial_out_bit equ 2 125 ; constant serial_in_bit 3 126 0003 serial_in_bit equ 3 127 ; comment {Define pin assignments and directions :} 128 ; comment {Techically , the pins are all read_write_manual , but it} 129 ; comment {is easier to do all of the tris register manipulation} 130 ; comment {by hand rather than using uCL { direction } commands . We} 131 ; comment {start with all the I / O pins set to read - only until such} 132 ; comment {time as the user explicitly sets them to outputs :} 133 0006 portb equ 6 134 0007 portc equ 7 135 0006 io9__byte equ 6 136 0001 io9__bit equ 1 137 0006 io8__byte equ 6 138 0000 io8__bit equ 0 139 0006 io7__byte equ 6 140 0005 io7__bit equ 5 141 0006 io6__byte equ 6 142 0004 io6__bit equ 4 143 0007 io5__byte equ 7 144 0005 io5__bit equ 5 145 0007 io4__byte equ 7 146 0004 io4__bit equ 4 147 0007 io3__byte equ 7 148 0003 io3__bit equ 3 149 0007 io2__byte equ 7 150 0002 io2__bit equ 2 151 0007 io1__byte equ 7 152 0001 io1__bit equ 1 153 0007 io0__byte equ 7 154 0000 io0__bit equ 0 155 0006 serial_out__byte equ 6 156 0002 serial_out__bit equ 2 157 0006 serial_in__byte equ 6 158 0003 serial_in__bit equ 3 159 ; constant mask 0x1f 160 001f mask equ 31 161 ; string_constants Start 162 ; Switch from register bank 1 to register bank 0 163 008 4a4 bcf rp0___byte,rp0___bit 164 ; Register bank is now 0 165 ; Switch from code bank 1 to code bank 0 before possible transfer (label) 166 009 4a3 bcf pa0___byte,pa0___bit 167 string___fetch: 168 00a 022 movwf pcl___register 169 ; id = 1 , 0 , 13 , 1 , 0 , 0 , 0 , 0 , 0r'16' , 8 , 0s'InOut10B' , 15 , 0s'Gramlich&Benson' 170 0000 id___string equ 0 171 id: 172 00b 1e2 addwf pcl___register,f 173 ; Length = 49 174 00c 831 retlw 49 175 ; 1 176 00d 801 retlw 1 177 ; 0 178 00e 800 retlw 0 179 ; 13 180 00f 80d retlw 13 181 ; 1 182 010 801 retlw 1 183 ; 0 184 011 800 retlw 0 185 ; 0 186 012 800 retlw 0 187 ; 0 188 013 800 retlw 0 189 ; 0 190 014 800 retlw 0 191 ; 0r'16' 192 015 86f retlw 111 ; random number 193 016 876 retlw 118 ; random number 194 017 8ca retlw 202 ; random number 195 018 8a4 retlw 164 ; random number 196 019 8a1 retlw 161 ; random number 197 01a 8e5 retlw 229 ; random number 198 01b 872 retlw 114 ; random number 199 01c 8ad retlw 173 ; random number 200 01d 852 retlw 82 ; random number 201 01e 8d2 retlw 210 ; random number 202 01f 8d1 retlw 209 ; random number 203 020 8db retlw 219 ; random number 204 021 8d1 retlw 209 ; random number 205 022 89c retlw 156 ; random number 206 023 84d retlw 77 ; random number 207 024 815 retlw 21 ; random number 208 ; 8 209 025 808 retlw 8 210 ; `InOut10B' 211 026 849 retlw 73 212 027 86e retlw 110 213 028 84f retlw 79 214 029 875 retlw 117 215 02a 874 retlw 116 216 02b 831 retlw 49 217 02c 830 retlw 48 218 02d 842 retlw 66 219 ; 15 220 02e 80f retlw 15 221 ; `Gramlich&Benson' 222 02f 847 retlw 71 223 030 872 retlw 114 224 031 861 retlw 97 225 032 86d retlw 109 226 033 86c retlw 108 227 034 869 retlw 105 228 035 863 retlw 99 229 036 868 retlw 104 230 037 826 retlw 38 231 038 842 retlw 66 232 039 865 retlw 101 233 03a 86e retlw 110 234 03b 873 retlw 115 235 03c 86f retlw 111 236 03d 86e retlw 110 237 ; string__constants End 238 ; comment {Some globals : byte} 239 0008 raw_low equ global__variables__bank0+0 240 0009 raw_high equ global__variables__bank0+1 241 000a inputs_low equ global__variables__bank0+2 242 000b inputs_high equ global__variables__bank0+3 243 000c outputs_low equ global__variables__bank0+4 244 000d outputs_high equ global__variables__bank0+5 245 000e complement_low equ global__variables__bank0+6 246 000f complement_high equ global__variables__bank0+7 247 0010 low_low equ global__variables__bank0+8 248 0011 low_high equ global__variables__bank0+9 249 0012 high_low equ global__variables__bank0+10 250 0013 high_high equ global__variables__bank0+11 251 0014 raising_low equ global__variables__bank0+12 252 0015 raising_high equ global__variables__bank0+13 253 0016 falling_low equ global__variables__bank0+14 254 0017 falling_high equ global__variables__bank0+15 255 0018 temporary equ global__variables__bank0+16 256 001e interrupt_enable equ global__bit__variables__bank0+0 257 001e interrupt_enable__byte equ global__bit__variables__bank0+0 258 0000 interrupt_enable__bit equ 0 259 001e interrupt_pending equ global__bit__variables__bank0+0 260 001e interrupt_pending__byte equ global__bit__variables__bank0+0 261 0001 interrupt_pending__bit equ 1 262 001e receiving equ global__bit__variables__bank0+0 263 001e receiving__byte equ global__bit__variables__bank0+0 264 0002 receiving__bit equ 2 265 ; bank 1 266 ; Default register bank is now 1 267 0030 direction_low equ global__variables__bank1+0 268 0031 direction_high equ global__variables__bank1+1 269 0032 glitch equ global__variables__bank1+2 270 0033 index equ global__variables__bank1+3 271 ; comment {Note that the 12 - bit PIC ' s only have a 2 - level deep stack .} 272 ; comment {The code starts in the main procedure < located at the end of this code >} 273 ; comment {The next level of procedure call is either get_byte or send_byte .} 274 ; comment {Lastly , the lowest level of procedure call is delay . It all fits ,} 275 ; comment {but just barely .} 276 277 ; procedure get_byte start 278 get_byte: 279 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 280 ; Procedure must be called with PCLATH set to code bank 0 281 0034 get_byte__variables__base equ global__variables__bank1+4 282 0034 get_byte__bytes__base equ get_byte__variables__base+0 283 0037 get_byte__bits__base equ get_byte__variables__base+3 284 0003 get_byte__total__bytes equ 3 285 ; arguments_none 286 0034 get_byte__0return__byte equ get_byte__bytes__base+0 287 ; This procedure will wait for a byte to be received from 288 ; serial_in_bit . It calls the delay procedure for all delays . 289 0035 get_byte__count equ get_byte__bytes__base+1 290 0036 get_byte__char equ get_byte__bytes__base+2 291 ; Why does the delay procedure wait for a third of bit ? Well , it 292 ; has to do with the loop immediately below . If we catch the 293 ; start bit at the beginning of a 1 / 3 bit time , we will be 294 ; sampling data at approximately 1 / 3 of the way into each bit . 295 ; Conversely , if we catch the start near the end of a 1 / 3 bit 296 ; bit time , we will be sampling data at approximately 2 / 3 of the 297 ; way into each bit . So , what this means is that our bit sample 298 ; times will be somewhere between 1 / 3 and 2 / 3 of bit < i . e . in 299 ; the middle of the bit . 300 ; It would be nice to tweak the code to shorter delay times 301 ; < 1 / 4 bit , 1 / 5 bit , etc . > but then it gets too hard to get 302 ; the bookeeping done in the delay routine . A 12 - bit PIC 303 ; running at 4 MHz <= 1 MIPS > , only has 138 instructions available 304 ; for the delay routine when at 1 / 3 of bit . 305 ; Wait for a start bit : 306 ; receiving := 1 307 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 308 03e 4a4 bcf rp0___byte,rp0___bit 309 ; Register bank is now 0 310 03f 55e bsf receiving__byte,receiving__bit 311 ; `while serial_in ...' start 312 ; Switch from register bank 0 to register bank 1 313 040 5a4 bsf rp0___byte,rp0___bit 314 ; Register bank is now 1 315 get_byte__155while__continue: 316 ; expression=`serial_in' exp_delay=0 true_delay=1 false_delay=2 true_size=2 false_size=1 317 041 766 btfss serial_in__byte,serial_in__bit 318 042 a47 goto get_byte__155while__break 319 ; call delay {{ }} 320 ; Switch from register bank 1 to register bank 0 321 043 4a4 bcf rp0___byte,rp0___bit 322 ; Register bank is now 0 323 044 9d5 call delay 324 ; Switch from register bank 0 to register bank 1 325 045 5a4 bsf rp0___byte,rp0___bit 326 ; Register bank is now 1 327 046 a41 goto get_byte__155while__continue 328 ; if exp=`serial_in' false goto 329 ; Other expression=`serial_in' delay=-1 330 get_byte__155while__break: 331 ; `while serial_in ...' end 332 ; Clear interrupt : 333 ; 1 cycle : 334 ; serial_out := 1 335 047 546 bsf serial_out__byte,serial_out__bit 336 ; Skip over start bit : 337 ; call delay {{ }} 338 ; Switch from register bank 1 to register bank 0 339 048 4a4 bcf rp0___byte,rp0___bit 340 ; Register bank is now 0 341 049 9d5 call delay 342 ; call delay {{ }} 343 04a 9d5 call delay 344 ; call delay {{ }} 345 04b 9d5 call delay 346 ; Sample in the middle third of each data bit ; 347 ; 1 cycle : 348 ; char := 0 349 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 350 04c 5a4 bsf rp0___byte,rp0___bit 351 ; Register bank is now 1 352 04d 076 clrf get_byte__char 353 ; 2 cycles to set up loop : 354 ; 1 + 1 + 2 = 4 355 ; nop extra_instructions_per_bit - 4 356 ; Delay 5 cycles 357 04e 000 nop 358 04f 000 nop 359 050 000 nop 360 051 000 nop 361 052 000 nop 362 ; `count_down count 8 ...' start 363 053 c08 movlw 8 364 054 035 movwf get_byte__count 365 get_byte__174_loop: 366 ; call delay {{ }} 367 ; Switch from register bank 1 to register bank 0 368 055 4a4 bcf rp0___byte,rp0___bit 369 ; Register bank is now 0 370 056 9d5 call delay 371 ; 2 cycles : 372 ; char := char >> 1 373 057 403 bcf c___byte,c___bit 374 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 375 058 5a4 bsf rp0___byte,rp0___bit 376 ; Register bank is now 1 377 059 336 rrf get_byte__char,f 378 ; 2 cycles : 379 ; if { serial_in } start 380 ; expression=`{ serial_in }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 381 05a 666 btfsc serial_in__byte,serial_in__bit 382 ; if { serial_in } body start 383 ; char @ 7 := 1 384 ; Select char @ 7 385 0036 get_byte__char__180select0 equ get_byte__char+0 386 0036 get_byte__char__180select0__byte equ get_byte__char+0 387 0007 get_byte__char__180select0__bit equ 7 388 05b 5f6 bsf get_byte__char__180select0__byte,get_byte__char__180select0__bit 389 ; if { serial_in } body end 390 ; if exp=`serial_in' false skip delay=2 391 ; Other expression=`{ serial_in }' delay=2 392 ; if { serial_in } end 393 ; call delay {{ }} 394 ; Switch from register bank 1 to register bank 0 395 05c 4a4 bcf rp0___byte,rp0___bit 396 ; Register bank is now 0 397 05d 9d5 call delay 398 ; call delay {{ }} 399 05e 9d5 call delay 400 ; 3 cycles at end of loop : 401 ; 2 + 2 + 3 = 7 402 ; nop extra_instructions_per_bit - 7 403 ; Delay 2 cycles 404 05f 000 nop 405 060 000 nop 406 ; Switch from register bank 0 to register bank 1 (which contains get_byte__count) 407 061 5a4 bsf rp0___byte,rp0___bit 408 ; Register bank is now 1 409 062 2f5 decfsz get_byte__count,f 410 063 a55 goto get_byte__174_loop 411 get_byte__174_done: 412 ; `count_down count 8 ...' end 413 ; Skip over 2 / 3 ' s of stop bit : 414 ; call delay {{ }} 415 ; Switch from register bank 1 to register bank 0 416 064 4a4 bcf rp0___byte,rp0___bit 417 ; Register bank is now 0 418 065 9d5 call delay 419 ; call delay {{ }} 420 066 9d5 call delay 421 ; return char 422 ; Switch from register bank 0 to register bank 1 (which contains get_byte__char) 423 067 5a4 bsf rp0___byte,rp0___bit 424 ; Register bank is now 1 425 068 216 movf get_byte__char,w 426 069 034 movwf get_byte__0return__byte 427 06a 800 retlw 0 428 ; procedure get_byte end 429 430 ; procedure send_byte start 431 send_byte: 432 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 433 ; Procedure must be called with PCLATH set to code bank 0 434 0037 send_byte__variables__base equ global__variables__bank1+7 435 0037 send_byte__bytes__base equ send_byte__variables__base+0 436 0039 send_byte__bits__base equ send_byte__variables__base+2 437 0002 send_byte__total__bytes equ 2 438 0037 send_byte__char equ send_byte__bytes__base+0 439 ; Send < char > to < tx > : 440 0038 send_byte__count equ send_byte__bytes__base+1 441 ; < receiving > will be 1 if the last get / put routine was a get . 442 ; Before we start transmitting a response back , we want to ensure 443 ; that there has been enough time to turn the line around . 444 ; We delay the first 1 / 3 of a bit to pad out the 9 - 2 / 3 bits from 445 ; for get_byte to 10 bits . We delay another 1 / 3 of a bit just 446 ; for good measure . Technically , the second call to delay < > 447 ; is not really needed . 448 ; if { receiving } start 449 ; expression=`{ receiving }' exp_delay=0 true_delay=-1 false_delay=0 true_size=3 false_size=0 450 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 451 06b 4a4 bcf rp0___byte,rp0___bit 452 ; Register bank is now 0 453 06c 443 bcf z___byte,z___bit 454 06d 65e btfsc receiving__byte,receiving__bit 455 06e 543 bsf z___byte,z___bit 456 ; Switch from register bank 0 to register bank 1 457 06f 5a4 bsf rp0___byte,rp0___bit 458 ; Register bank is now 1 459 070 743 btfss z___byte,z___bit 460 071 a77 goto label210__0end 461 ; if { receiving } body start 462 ; receiving := 0 463 ; Switch from register bank 1 to register bank 0 (which contains receiving__byte) 464 072 4a4 bcf rp0___byte,rp0___bit 465 ; Register bank is now 0 466 073 45e bcf receiving__byte,receiving__bit 467 ; call delay {{ }} 468 074 9d5 call delay 469 ; call delay {{ }} 470 075 9d5 call delay 471 ; if { receiving } body end 472 ; Switch from register bank 0 to register bank 1 473 076 5a4 bsf rp0___byte,rp0___bit 474 ; Register bank is now 1 475 label210__0end: 476 ; if exp=`receiving' empty false 477 ; Other expression=`{ receiving }' delay=-1 478 ; if { receiving } end 479 ; Send the start bit : 480 ; 1 cycle : 481 ; serial_out := 0 482 077 446 bcf serial_out__byte,serial_out__bit 483 ; call delay {{ }} 484 ; Switch from register bank 1 to register bank 0 485 078 4a4 bcf rp0___byte,rp0___bit 486 ; Register bank is now 0 487 079 9d5 call delay 488 ; call delay {{ }} 489 07a 9d5 call delay 490 ; call delay {{ }} 491 07b 9d5 call delay 492 ; 2 cycles to set up loop : 493 ; 1 + 2 = 3 494 ; nop extra_instructions_per_bit - 3 495 ; Delay 6 cycles 496 07c 000 nop 497 07d 000 nop 498 07e 000 nop 499 07f 000 nop 500 080 000 nop 501 081 000 nop 502 ; Send the data : 503 ; `count_down count 8 ...' start 504 082 c08 movlw 8 505 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 506 083 5a4 bsf rp0___byte,rp0___bit 507 ; Register bank is now 1 508 084 038 movwf send_byte__count 509 send_byte__228_loop: 510 ; 4 cycles : 511 ; serial_out := char @ 0 512 ; Alias variable for select char @ 0 513 0037 send_byte__char__230select0 equ send_byte__char+0 514 0037 send_byte__char__230select0__byte equ send_byte__char+0 515 0000 send_byte__char__230select0__bit equ 0 516 085 717 btfss send_byte__char__230select0__byte,send_byte__char__230select0__bit 517 086 446 bcf serial_out__byte,serial_out__bit 518 087 617 btfsc send_byte__char__230select0__byte,send_byte__char__230select0__bit 519 088 546 bsf serial_out__byte,serial_out__bit 520 ; 2 cycles : 521 ; char := char >> 1 522 089 403 bcf c___byte,c___bit 523 08a 337 rrf send_byte__char,f 524 ; call delay {{ }} 525 ; Switch from register bank 1 to register bank 0 526 08b 4a4 bcf rp0___byte,rp0___bit 527 ; Register bank is now 0 528 08c 9d5 call delay 529 ; call delay {{ }} 530 08d 9d5 call delay 531 ; call delay {{ }} 532 08e 9d5 call delay 533 ; 3 cycles at end of loop : 534 ; 4 + 2 + 3 = 9 = no NOP ' s needed : 535 ; Switch from register bank 0 to register bank 1 (which contains send_byte__count) 536 08f 5a4 bsf rp0___byte,rp0___bit 537 ; Register bank is now 1 538 090 2f8 decfsz send_byte__count,f 539 091 a85 goto send_byte__228_loop 540 send_byte__228_done: 541 ; `count_down count 8 ...' end 542 ; Send the stop bit : 543 ; nop 1 544 ; Delay 1 cycles 545 092 000 nop 546 ; 1 cycle 547 ; serial_out := 1 548 093 546 bsf serial_out__byte,serial_out__bit 549 ; call delay {{ }} 550 ; Switch from register bank 1 to register bank 0 551 094 4a4 bcf rp0___byte,rp0___bit 552 ; Register bank is now 0 553 095 9d5 call delay 554 ; call delay {{ }} 555 096 9d5 call delay 556 ; call delay {{ }} 557 097 9d5 call delay 558 ; 2 cycles for call / return 559 ; 2 cycles for argument 560 ; 1 + 2 + 2 = 5 561 ; nop extra_instructions_per_bit - 5 562 ; Delay 4 cycles 563 098 000 nop 564 099 000 nop 565 09a 000 nop 566 09b 000 nop 567 ; procedure send_byte end 568 ; Switch from register bank 0 to register bank 1 569 09c 5a4 bsf rp0___byte,rp0___bit 570 ; Register bank is now 1 571 09d 800 retlw 0 572 ; bank 1 573 ; Default register bank is now 1 574 575 ; procedure direction_set start 576 direction_set: 577 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 578 ; Procedure must be called with PCLATH set to code bank 0 579 0039 direction_set__variables__base equ global__variables__bank1+9 580 0039 direction_set__bytes__base equ direction_set__variables__base+0 581 003a direction_set__bits__base equ direction_set__variables__base+1 582 0001 direction_set__total__bytes equ 1 583 ; arguments_none 584 ; This procedure will set the direction appropriately . 585 0039 direction_set__temp equ direction_set__bytes__base+0 586 ; Deal with port C : 587 ; temp := 0 588 09e 079 clrf direction_set__temp 589 ; if { direction_low @ 0 } start 590 ; Alias variable for select direction_low @ 0 591 0030 direction_low__265select0 equ direction_low+0 592 0030 direction_low__265select0__byte equ direction_low+0 593 0000 direction_low__265select0__bit equ 0 594 ; expression=`{ direction_low @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 595 09f 610 btfsc direction_low__265select0__byte,direction_low__265select0__bit 596 ; if { direction_low @ 0 } body start 597 ; temp @ io0_bit := 1 598 ; Select temp @ io0_bit 599 0039 direction_set__temp__266select0 equ direction_set__temp+0 600 0039 direction_set__temp__266select0__byte equ direction_set__temp+0 601 0000 direction_set__temp__266select0__bit equ 0 602 0a0 519 bsf direction_set__temp__266select0__byte,direction_set__temp__266select0__bit 603 ; if { direction_low @ 0 } body end 604 ; if exp=` direction_low @ 0 ' false skip delay=2 605 ; Other expression=`{ direction_low @ 0 }' delay=2 606 ; if { direction_low @ 0 } end 607 ; if { direction_low @ 1 } start 608 ; Alias variable for select direction_low @ 1 609 0030 direction_low__268select0 equ direction_low+0 610 0030 direction_low__268select0__byte equ direction_low+0 611 0001 direction_low__268select0__bit equ 1 612 ; expression=`{ direction_low @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 613 0a1 630 btfsc direction_low__268select0__byte,direction_low__268select0__bit 614 ; if { direction_low @ 1 } body start 615 ; temp @ io1_bit := 1 616 ; Select temp @ io1_bit 617 0039 direction_set__temp__269select0 equ direction_set__temp+0 618 0039 direction_set__temp__269select0__byte equ direction_set__temp+0 619 0001 direction_set__temp__269select0__bit equ 1 620 0a2 539 bsf direction_set__temp__269select0__byte,direction_set__temp__269select0__bit 621 ; if { direction_low @ 1 } body end 622 ; if exp=` direction_low @ 1 ' false skip delay=2 623 ; Other expression=`{ direction_low @ 1 }' delay=2 624 ; if { direction_low @ 1 } end 625 ; if { direction_low @ 2 } start 626 ; Alias variable for select direction_low @ 2 627 0030 direction_low__271select0 equ direction_low+0 628 0030 direction_low__271select0__byte equ direction_low+0 629 0002 direction_low__271select0__bit equ 2 630 ; expression=`{ direction_low @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 631 0a3 650 btfsc direction_low__271select0__byte,direction_low__271select0__bit 632 ; if { direction_low @ 2 } body start 633 ; temp @ io2_bit := 1 634 ; Select temp @ io2_bit 635 0039 direction_set__temp__272select0 equ direction_set__temp+0 636 0039 direction_set__temp__272select0__byte equ direction_set__temp+0 637 0002 direction_set__temp__272select0__bit equ 2 638 0a4 559 bsf direction_set__temp__272select0__byte,direction_set__temp__272select0__bit 639 ; if { direction_low @ 2 } body end 640 ; if exp=` direction_low @ 2 ' false skip delay=2 641 ; Other expression=`{ direction_low @ 2 }' delay=2 642 ; if { direction_low @ 2 } end 643 ; if { direction_low @ 3 } start 644 ; Alias variable for select direction_low @ 3 645 0030 direction_low__274select0 equ direction_low+0 646 0030 direction_low__274select0__byte equ direction_low+0 647 0003 direction_low__274select0__bit equ 3 648 ; expression=`{ direction_low @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 649 0a5 670 btfsc direction_low__274select0__byte,direction_low__274select0__bit 650 ; if { direction_low @ 3 } body start 651 ; temp @ io3_bit := 1 652 ; Select temp @ io3_bit 653 0039 direction_set__temp__275select0 equ direction_set__temp+0 654 0039 direction_set__temp__275select0__byte equ direction_set__temp+0 655 0003 direction_set__temp__275select0__bit equ 3 656 0a6 579 bsf direction_set__temp__275select0__byte,direction_set__temp__275select0__bit 657 ; if { direction_low @ 3 } body end 658 ; if exp=` direction_low @ 3 ' false skip delay=2 659 ; Other expression=`{ direction_low @ 3 }' delay=2 660 ; if { direction_low @ 3 } end 661 ; if { direction_low @ 4 } start 662 ; Alias variable for select direction_low @ 4 663 0030 direction_low__277select0 equ direction_low+0 664 0030 direction_low__277select0__byte equ direction_low+0 665 0004 direction_low__277select0__bit equ 4 666 ; expression=`{ direction_low @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 667 0a7 690 btfsc direction_low__277select0__byte,direction_low__277select0__bit 668 ; if { direction_low @ 4 } body start 669 ; temp @ io4_bit := 1 670 ; Select temp @ io4_bit 671 0039 direction_set__temp__278select0 equ direction_set__temp+0 672 0039 direction_set__temp__278select0__byte equ direction_set__temp+0 673 0004 direction_set__temp__278select0__bit equ 4 674 0a8 599 bsf direction_set__temp__278select0__byte,direction_set__temp__278select0__bit 675 ; if { direction_low @ 4 } body end 676 ; if exp=` direction_low @ 4 ' false skip delay=2 677 ; Other expression=`{ direction_low @ 4 }' delay=2 678 ; if { direction_low @ 4 } end 679 ; if { direction_high @ 0 } start 680 ; Alias variable for select direction_high @ 0 681 0031 direction_high__280select0 equ direction_high+0 682 0031 direction_high__280select0__byte equ direction_high+0 683 0000 direction_high__280select0__bit equ 0 684 ; expression=`{ direction_high @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 685 0a9 611 btfsc direction_high__280select0__byte,direction_high__280select0__bit 686 ; if { direction_high @ 0 } body start 687 ; temp @ io5_bit := 1 688 ; Select temp @ io5_bit 689 0039 direction_set__temp__281select0 equ direction_set__temp+0 690 0039 direction_set__temp__281select0__byte equ direction_set__temp+0 691 0005 direction_set__temp__281select0__bit equ 5 692 0aa 5b9 bsf direction_set__temp__281select0__byte,direction_set__temp__281select0__bit 693 ; if { direction_high @ 0 } body end 694 ; if exp=` direction_high @ 0 ' false skip delay=2 695 ; Other expression=`{ direction_high @ 0 }' delay=2 696 ; if { direction_high @ 0 } end 697 ; inline assembly statements begin 698 0ab 219 movf direction_set__temp,w 699 0ac 007 tris 7 700 ; inline assembly statements end 701 ; Deal with port B : 702 ; temp := 0 703 0ad 079 clrf direction_set__temp 704 ; if { direction_high @ 1 } start 705 ; Alias variable for select direction_high @ 1 706 0031 direction_high__290select0 equ direction_high+0 707 0031 direction_high__290select0__byte equ direction_high+0 708 0001 direction_high__290select0__bit equ 1 709 ; expression=`{ direction_high @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 710 0ae 631 btfsc direction_high__290select0__byte,direction_high__290select0__bit 711 ; if { direction_high @ 1 } body start 712 ; temp @ io6_bit := 1 713 ; Select temp @ io6_bit 714 0039 direction_set__temp__291select0 equ direction_set__temp+0 715 0039 direction_set__temp__291select0__byte equ direction_set__temp+0 716 0004 direction_set__temp__291select0__bit equ 4 717 0af 599 bsf direction_set__temp__291select0__byte,direction_set__temp__291select0__bit 718 ; if { direction_high @ 1 } body end 719 ; if exp=` direction_high @ 1 ' false skip delay=2 720 ; Other expression=`{ direction_high @ 1 }' delay=2 721 ; if { direction_high @ 1 } end 722 ; if { direction_high @ 2 } start 723 ; Alias variable for select direction_high @ 2 724 0031 direction_high__293select0 equ direction_high+0 725 0031 direction_high__293select0__byte equ direction_high+0 726 0002 direction_high__293select0__bit equ 2 727 ; expression=`{ direction_high @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 728 0b0 651 btfsc direction_high__293select0__byte,direction_high__293select0__bit 729 ; if { direction_high @ 2 } body start 730 ; temp @ io7_bit := 1 731 ; Select temp @ io7_bit 732 0039 direction_set__temp__294select0 equ direction_set__temp+0 733 0039 direction_set__temp__294select0__byte equ direction_set__temp+0 734 0005 direction_set__temp__294select0__bit equ 5 735 0b1 5b9 bsf direction_set__temp__294select0__byte,direction_set__temp__294select0__bit 736 ; if { direction_high @ 2 } body end 737 ; if exp=` direction_high @ 2 ' false skip delay=2 738 ; Other expression=`{ direction_high @ 2 }' delay=2 739 ; if { direction_high @ 2 } end 740 ; if { direction_high @ 3 } start 741 ; Alias variable for select direction_high @ 3 742 0031 direction_high__296select0 equ direction_high+0 743 0031 direction_high__296select0__byte equ direction_high+0 744 0003 direction_high__296select0__bit equ 3 745 ; expression=`{ direction_high @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 746 0b2 671 btfsc direction_high__296select0__byte,direction_high__296select0__bit 747 ; if { direction_high @ 3 } body start 748 ; temp @ io8_bit := 1 749 ; Select temp @ io8_bit 750 0039 direction_set__temp__297select0 equ direction_set__temp+0 751 0039 direction_set__temp__297select0__byte equ direction_set__temp+0 752 0000 direction_set__temp__297select0__bit equ 0 753 0b3 519 bsf direction_set__temp__297select0__byte,direction_set__temp__297select0__bit 754 ; if { direction_high @ 3 } body end 755 ; if exp=` direction_high @ 3 ' false skip delay=2 756 ; Other expression=`{ direction_high @ 3 }' delay=2 757 ; if { direction_high @ 3 } end 758 ; if { direction_high @ 4 } start 759 ; Alias variable for select direction_high @ 4 760 0031 direction_high__299select0 equ direction_high+0 761 0031 direction_high__299select0__byte equ direction_high+0 762 0004 direction_high__299select0__bit equ 4 763 ; expression=`{ direction_high @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 764 0b4 691 btfsc direction_high__299select0__byte,direction_high__299select0__bit 765 ; if { direction_high @ 4 } body start 766 ; temp @ io9_bit := 1 767 ; Select temp @ io9_bit 768 0039 direction_set__temp__300select0 equ direction_set__temp+0 769 0039 direction_set__temp__300select0__byte equ direction_set__temp+0 770 0001 direction_set__temp__300select0__bit equ 1 771 0b5 539 bsf direction_set__temp__300select0__byte,direction_set__temp__300select0__bit 772 ; if { direction_high @ 4 } body end 773 ; if exp=` direction_high @ 4 ' false skip delay=2 774 ; Other expression=`{ direction_high @ 4 }' delay=2 775 ; if { direction_high @ 4 } end 776 ; temp @ serial_in_bit := 1 777 ; Select temp @ serial_in_bit 778 0039 direction_set__temp__302select0 equ direction_set__temp+0 779 0039 direction_set__temp__302select0__byte equ direction_set__temp+0 780 0003 direction_set__temp__302select0__bit equ 3 781 0b6 579 bsf direction_set__temp__302select0__byte,direction_set__temp__302select0__bit 782 ; inline assembly statements begin 783 0b7 219 movf direction_set__temp,w 784 0b8 006 tris 6 785 ; inline assembly statements end 786 ; procedure direction_set end 787 0b9 800 retlw 0 788 789 ; procedure reset start 790 reset: 791 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 792 ; Procedure must be called with PCLATH set to code bank 0 793 003a reset__variables__base equ global__variables__bank1+10 794 003a reset__bytes__base equ reset__variables__base+0 795 003a reset__bits__base equ reset__variables__base+0 796 0000 reset__total__bytes equ 0 797 ; arguments_none 798 ; This procedure will initialize all global registers : 799 ; Initialize global registers : 800 ; inputs_low := 0 801 0ba 06a clrf inputs_low 802 ; inputs_high := 0 803 0bb 06b clrf inputs_high 804 ; raw_low := 0 805 0bc 068 clrf raw_low 806 ; raw_high := 0 807 0bd 069 clrf raw_high 808 ; outputs_low := 0 809 0be 06c clrf outputs_low 810 ; outputs_high := 0 811 0bf 06d clrf outputs_high 812 ; complement_low := 0 813 0c0 06e clrf complement_low 814 ; complement_high := 0 815 0c1 06f clrf complement_high 816 ; direction_low := mask 817 0c2 c1f movlw 31 818 0c3 030 movwf direction_low 819 ; direction_high := mask 820 0c4 c1f movlw 31 821 0c5 031 movwf direction_high 822 ; low_low := 0 823 ; Switch from register bank 1 to register bank 0 (which contains low_low) 824 0c6 4a4 bcf rp0___byte,rp0___bit 825 ; Register bank is now 0 826 0c7 070 clrf low_low 827 ; low_high := 0 828 0c8 071 clrf low_high 829 ; high_low := 0 830 0c9 072 clrf high_low 831 ; high_high := 0 832 0ca 073 clrf high_high 833 ; raising_low := 0 834 0cb 074 clrf raising_low 835 ; raising_high := 0 836 0cc 075 clrf raising_high 837 ; falling_low := 0 838 0cd 076 clrf falling_low 839 ; falling_high := 0 840 0ce 077 clrf falling_high 841 ; interrupt_enable := 0 842 0cf 41e bcf interrupt_enable__byte,interrupt_enable__bit 843 ; interrupt_pending := 0 844 0d0 43e bcf interrupt_pending__byte,interrupt_pending__bit 845 ; Initialize remaining registers : 846 ; glitch := 0 847 ; Switch from register bank 0 to register bank 1 (which contains glitch) 848 0d1 5a4 bsf rp0___byte,rp0___bit 849 ; Register bank is now 1 850 0d2 072 clrf glitch 851 ; index := 0 852 0d3 073 clrf index 853 ; procedure reset end 854 0d4 800 retlw 0 855 ; bank 0 856 ; Default register bank is now 0 857 858 ; procedure delay start 859 ; optimize 0 860 delay: 861 ; Procedure must be called with RP0, RP1, and IRP set to register bank 0 862 ; Procedure must be called with PCLATH set to code bank 0 863 0019 delay__variables__base equ global__variables__bank0+17 864 0019 delay__bytes__base equ delay__variables__base+0 865 001d delay__bits__base equ delay__variables__base+4 866 0005 delay__total__bytes equ 5 867 001c delay__344byte1 equ delay__bytes__base+3 868 001c delay__408byte0 equ delay__bytes__base+3 869 001c delay__409byte0 equ delay__bytes__base+3 870 001d delay__386bit1 equ delay__bits__base+0 871 001d delay__386bit1__byte equ delay__bits__base+0 872 0003 delay__386bit1__bit equ 3 873 001d delay__379bit1 equ delay__bits__base+0 874 001d delay__379bit1__byte equ delay__bits__base+0 875 0003 delay__379bit1__bit equ 3 876 ; arguments_none 877 ; uniform_delay delay_instructions 878 ; Uniform delay remaining = 131 Accumulated Delay = 0 879 ; Uniform delay remaining = 131 Accumulated Delay = 0 880 ; This procedure delays 1 / 3 of a bit . 881 ; Uniform delay remaining = 131 Accumulated Delay = 0 882 ; Uniform delay remaining = 131 Accumulated Delay = 0 883 0019 delay__previous_low equ delay__bytes__base+0 884 ; Uniform delay remaining = 131 Accumulated Delay = 0 885 001a delay__previous_high equ delay__bytes__base+1 886 ; Uniform delay remaining = 131 Accumulated Delay = 0 887 001b delay__temp equ delay__bytes__base+2 888 ; Uniform delay remaining = 131 Accumulated Delay = 0 889 ; Uniform delay remaining = 131 Accumulated Delay = 0 890 ; Kick the dog : 891 ; Uniform delay remaining = 131 Accumulated Delay = 0 892 ; watch_dog_reset 893 0d5 004 clrwdt 894 ; Uniform delay remaining = 130 Accumulated Delay = 1 895 ; Uniform delay remaining = 130 Accumulated Delay = 1 896 ; Set the port C outputs first : 897 ; Uniform delay remaining = 130 Accumulated Delay = 1 898 ; temp := outputs_low 899 0d6 20c movf outputs_low,w 900 0d7 03b movwf delay__temp 901 ; Uniform delay remaining = 128 Accumulated Delay = 3 902 ; if { outputs_high @ 0 } start 903 ; Alias variable for select outputs_high @ 0 904 000d outputs_high__360select0 equ outputs_high+0 905 000d outputs_high__360select0__byte equ outputs_high+0 906 0000 outputs_high__360select0__bit equ 0 907 ; expression=`{ outputs_high @ 0 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 908 0d8 60d btfsc outputs_high__360select0__byte,outputs_high__360select0__bit 909 ; if { outputs_high @ 0 } body start 910 ; Uniform delay remaining = 128 Accumulated Delay = 0 911 ; temp @ io5_bit := 1 912 ; Select temp @ io5_bit 913 001b delay__temp__361select0 equ delay__temp+0 914 001b delay__temp__361select0__byte equ delay__temp+0 915 0005 delay__temp__361select0__bit equ 5 916 0d9 5bb bsf delay__temp__361select0__byte,delay__temp__361select0__bit 917 ; Uniform delay remaining = 127 Accumulated Delay = 1 918 ; Uniform delay remaining = 127 Accumulated Delay = 1 919 ; if { outputs_high @ 0 } body end 920 ; if exp=` outputs_high @ 0 ' false skip delay=2 921 ; Other expression=`{ outputs_high @ 0 }' delay=2 922 ; if { outputs_high @ 0 } end 923 ; Uniform delay remaining = 126 Accumulated Delay = 5 924 ; portc := temp 925 0da 21b movf delay__temp,w 926 0db 027 movwf portc 927 ; Uniform delay remaining = 124 Accumulated Delay = 7 928 ; Uniform delay remaining = 124 Accumulated Delay = 7 929 ; Set the port outputs next : 930 ; Uniform delay remaining = 124 Accumulated Delay = 7 931 ; temp := 0 932 0dc 07b clrf delay__temp 933 ; Uniform delay remaining = 123 Accumulated Delay = 8 934 ; if { outputs_high @ 1 } start 935 ; Alias variable for select outputs_high @ 1 936 000d outputs_high__367select0 equ outputs_high+0 937 000d outputs_high__367select0__byte equ outputs_high+0 938 0001 outputs_high__367select0__bit equ 1 939 ; expression=`{ outputs_high @ 1 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 940 0dd 62d btfsc outputs_high__367select0__byte,outputs_high__367select0__bit 941 ; if { outputs_high @ 1 } body start 942 ; Uniform delay remaining = 123 Accumulated Delay = 0 943 ; temp @ io6_bit := 1 944 ; Select temp @ io6_bit 945 001b delay__temp__368select0 equ delay__temp+0 946 001b delay__temp__368select0__byte equ delay__temp+0 947 0004 delay__temp__368select0__bit equ 4 948 0de 59b bsf delay__temp__368select0__byte,delay__temp__368select0__bit 949 ; Uniform delay remaining = 122 Accumulated Delay = 1 950 ; Uniform delay remaining = 122 Accumulated Delay = 1 951 ; if { outputs_high @ 1 } body end 952 ; if exp=` outputs_high @ 1 ' false skip delay=2 953 ; Other expression=`{ outputs_high @ 1 }' delay=2 954 ; if { outputs_high @ 1 } end 955 ; Uniform delay remaining = 121 Accumulated Delay = 10 956 ; if { outputs_high @ 2 } start 957 ; Alias variable for select outputs_high @ 2 958 000d outputs_high__370select0 equ outputs_high+0 959 000d outputs_high__370select0__byte equ outputs_high+0 960 0002 outputs_high__370select0__bit equ 2 961 ; expression=`{ outputs_high @ 2 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 962 0df 64d btfsc outputs_high__370select0__byte,outputs_high__370select0__bit 963 ; if { outputs_high @ 2 } body start 964 ; Uniform delay remaining = 121 Accumulated Delay = 0 965 ; temp @ io7_bit := 1 966 ; Select temp @ io7_bit 967 001b delay__temp__371select0 equ delay__temp+0 968 001b delay__temp__371select0__byte equ delay__temp+0 969 0005 delay__temp__371select0__bit equ 5 970 0e0 5bb bsf delay__temp__371select0__byte,delay__temp__371select0__bit 971 ; Uniform delay remaining = 120 Accumulated Delay = 1 972 ; Uniform delay remaining = 120 Accumulated Delay = 1 973 ; if { outputs_high @ 2 } body end 974 ; if exp=` outputs_high @ 2 ' false skip delay=2 975 ; Other expression=`{ outputs_high @ 2 }' delay=2 976 ; if { outputs_high @ 2 } end 977 ; Uniform delay remaining = 119 Accumulated Delay = 12 978 ; if { outputs_high @ 3 } start 979 ; Alias variable for select outputs_high @ 3 980 000d outputs_high__373select0 equ outputs_high+0 981 000d outputs_high__373select0__byte equ outputs_high+0 982 0003 outputs_high__373select0__bit equ 3 983 ; expression=`{ outputs_high @ 3 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 984 0e1 66d btfsc outputs_high__373select0__byte,outputs_high__373select0__bit 985 ; if { outputs_high @ 3 } body start 986 ; Uniform delay remaining = 119 Accumulated Delay = 0 987 ; temp @ io8_bit := 1 988 ; Select temp @ io8_bit 989 001b delay__temp__374select0 equ delay__temp+0 990 001b delay__temp__374select0__byte equ delay__temp+0 991 0000 delay__temp__374select0__bit equ 0 992 0e2 51b bsf delay__temp__374select0__byte,delay__temp__374select0__bit 993 ; Uniform delay remaining = 118 Accumulated Delay = 1 994 ; Uniform delay remaining = 118 Accumulated Delay = 1 995 ; if { outputs_high @ 3 } body end 996 ; if exp=` outputs_high @ 3 ' false skip delay=2 997 ; Other expression=`{ outputs_high @ 3 }' delay=2 998 ; if { outputs_high @ 3 } end 999 ; Uniform delay remaining = 117 Accumulated Delay = 14 1000 ; if { outputs_high @ 4 } start 1001 ; Alias variable for select outputs_high @ 4 1002 000d outputs_high__376select0 equ outputs_high+0 1003 000d outputs_high__376select0__byte equ outputs_high+0 1004 0004 outputs_high__376select0__bit equ 4 1005 ; expression=`{ outputs_high @ 4 }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1006 0e3 68d btfsc outputs_high__376select0__byte,outputs_high__376select0__bit 1007 ; if { outputs_high @ 4 } body start 1008 ; Uniform delay remaining = 117 Accumulated Delay = 0 1009 ; temp @ io9_bit := 1 1010 ; Select temp @ io9_bit 1011 001b delay__temp__377select0 equ delay__temp+0 1012 001b delay__temp__377select0__byte equ delay__temp+0 1013 0001 delay__temp__377select0__bit equ 1 1014 0e4 53b bsf delay__temp__377select0__byte,delay__temp__377select0__bit 1015 ; Uniform delay remaining = 116 Accumulated Delay = 1 1016 ; Uniform delay remaining = 116 Accumulated Delay = 1 1017 ; if { outputs_high @ 4 } body end 1018 ; if exp=` outputs_high @ 4 ' false skip delay=2 1019 ; Other expression=`{ outputs_high @ 4 }' delay=2 1020 ; if { outputs_high @ 4 } end 1021 ; Uniform delay remaining = 115 Accumulated Delay = 16 1022 ; temp @ serial_out_bit := portb @ serial_out_bit 1023 ; Alias variable for select portb @ serial_out_bit 1024 0006 portb__379select2 equ portb+0 1025 0006 portb__379select2__byte equ portb+0 1026 0002 portb__379select2__bit equ 2 1027 0e5 47d bcf delay__379bit1__byte,delay__379bit1__bit 1028 0e6 646 btfsc portb__379select2__byte,portb__379select2__bit 1029 0e7 57d bsf delay__379bit1__byte,delay__379bit1__bit 1030 ; Select variable temp @ serial_out_bit 1031 001b delay__temp__379select3 equ delay__temp+0 1032 001b delay__temp__379select3__byte equ delay__temp+0 1033 0002 delay__temp__379select3__bit equ 2 1034 0e8 77d btfss delay__379bit1__byte,delay__379bit1__bit 1035 0e9 45b bcf delay__temp__379select3__byte,delay__temp__379select3__bit 1036 0ea 67d btfsc delay__379bit1__byte,delay__379bit1__bit 1037 0eb 55b bsf delay__temp__379select3__byte,delay__temp__379select3__bit 1038 ; Uniform delay remaining = 108 Accumulated Delay = 23 1039 ; portb := temp 1040 0ec 21b movf delay__temp,w 1041 0ed 026 movwf portb 1042 ; Uniform delay remaining = 106 Accumulated Delay = 25 1043 ; Uniform delay remaining = 106 Accumulated Delay = 25 1044 ; Now read inputs : 1045 ; Uniform delay remaining = 106 Accumulated Delay = 25 1046 ; temp := portc 1047 0ee 207 movf portc,w 1048 0ef 03b movwf delay__temp 1049 ; Uniform delay remaining = 104 Accumulated Delay = 27 1050 ; raw_low := temp & mask 1051 0f0 c1f movlw 31 1052 0f1 15b andwf delay__temp,w 1053 0f2 028 movwf raw_low 1054 ; Uniform delay remaining = 101 Accumulated Delay = 30 1055 ; raw_high := 0 1056 0f3 069 clrf raw_high 1057 ; Uniform delay remaining = 100 Accumulated Delay = 31 1058 ; raw_high @ 0 := temp @ 5 1059 ; Alias variable for select temp @ 5 1060 001b delay__temp__386select2 equ delay__temp+0 1061 001b delay__temp__386select2__byte equ delay__temp+0 1062 0005 delay__temp__386select2__bit equ 5 1063 0f4 47d bcf delay__386bit1__byte,delay__386bit1__bit 1064 0f5 6bb btfsc delay__temp__386select2__byte,delay__temp__386select2__bit 1065 0f6 57d bsf delay__386bit1__byte,delay__386bit1__bit 1066 ; Select variable raw_high @ 0 1067 0009 raw_high__386select3 equ raw_high+0 1068 0009 raw_high__386select3__byte equ raw_high+0 1069 0000 raw_high__386select3__bit equ 0 1070 0f7 77d btfss delay__386bit1__byte,delay__386bit1__bit 1071 0f8 409 bcf raw_high__386select3__byte,raw_high__386select3__bit 1072 0f9 67d btfsc delay__386bit1__byte,delay__386bit1__bit 1073 0fa 509 bsf raw_high__386select3__byte,raw_high__386select3__bit 1074 ; Uniform delay remaining = 93 Accumulated Delay = 38 1075 ; temp := portb 1076 0fb 206 movf portb,w 1077 0fc 03b movwf delay__temp 1078 ; Uniform delay remaining = 91 Accumulated Delay = 40 1079 ; if { temp @ io6_bit } start 1080 ; Alias variable for select temp @ io6_bit 1081 001b delay__temp__388select0 equ delay__temp+0 1082 001b delay__temp__388select0__byte equ delay__temp+0 1083 0004 delay__temp__388select0__bit equ 4 1084 ; expression=`{ temp @ io6_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1085 0fd 69b btfsc delay__temp__388select0__byte,delay__temp__388select0__bit 1086 ; if { temp @ io6_bit } body start 1087 ; Uniform delay remaining = 91 Accumulated Delay = 0 1088 ; raw_high @ 1 := 1 1089 ; Select raw_high @ 1 1090 0009 raw_high__389select0 equ raw_high+0 1091 0009 raw_high__389select0__byte equ raw_high+0 1092 0001 raw_high__389select0__bit equ 1 1093 0fe 529 bsf raw_high__389select0__byte,raw_high__389select0__bit 1094 ; Uniform delay remaining = 90 Accumulated Delay = 1 1095 ; Uniform delay remaining = 90 Accumulated Delay = 1 1096 ; if { temp @ io6_bit } body end 1097 ; if exp=` temp @ io6_bit ' false skip delay=2 1098 ; Other expression=`{ temp @ io6_bit }' delay=2 1099 ; if { temp @ io6_bit } end 1100 ; Uniform delay remaining = 89 Accumulated Delay = 42 1101 ; if { temp @ io7_bit } start 1102 ; Alias variable for select temp @ io7_bit 1103 001b delay__temp__391select0 equ delay__temp+0 1104 001b delay__temp__391select0__byte equ delay__temp+0 1105 0005 delay__temp__391select0__bit equ 5 1106 ; expression=`{ temp @ io7_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1107 0ff 6bb btfsc delay__temp__391select0__byte,delay__temp__391select0__bit 1108 ; if { temp @ io7_bit } body start 1109 ; Uniform delay remaining = 89 Accumulated Delay = 0 1110 ; raw_high @ 2 := 1 1111 ; Select raw_high @ 2 1112 0009 raw_high__392select0 equ raw_high+0 1113 0009 raw_high__392select0__byte equ raw_high+0 1114 0002 raw_high__392select0__bit equ 2 1115 100 549 bsf raw_high__392select0__byte,raw_high__392select0__bit 1116 ; Uniform delay remaining = 88 Accumulated Delay = 1 1117 ; Uniform delay remaining = 88 Accumulated Delay = 1 1118 ; if { temp @ io7_bit } body end 1119 ; if exp=` temp @ io7_bit ' false skip delay=2 1120 ; Other expression=`{ temp @ io7_bit }' delay=2 1121 ; if { temp @ io7_bit } end 1122 ; Uniform delay remaining = 87 Accumulated Delay = 44 1123 ; if { temp @ io8_bit } start 1124 ; Alias variable for select temp @ io8_bit 1125 001b delay__temp__394select0 equ delay__temp+0 1126 001b delay__temp__394select0__byte equ delay__temp+0 1127 0000 delay__temp__394select0__bit equ 0 1128 ; expression=`{ temp @ io8_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1129 101 61b btfsc delay__temp__394select0__byte,delay__temp__394select0__bit 1130 ; if { temp @ io8_bit } body start 1131 ; Uniform delay remaining = 87 Accumulated Delay = 0 1132 ; raw_high @ 3 := 1 1133 ; Select raw_high @ 3 1134 0009 raw_high__395select0 equ raw_high+0 1135 0009 raw_high__395select0__byte equ raw_high+0 1136 0003 raw_high__395select0__bit equ 3 1137 102 569 bsf raw_high__395select0__byte,raw_high__395select0__bit 1138 ; Uniform delay remaining = 86 Accumulated Delay = 1 1139 ; Uniform delay remaining = 86 Accumulated Delay = 1 1140 ; if { temp @ io8_bit } body end 1141 ; if exp=` temp @ io8_bit ' false skip delay=2 1142 ; Other expression=`{ temp @ io8_bit }' delay=2 1143 ; if { temp @ io8_bit } end 1144 ; Uniform delay remaining = 85 Accumulated Delay = 46 1145 ; if { temp @ io9_bit } start 1146 ; Alias variable for select temp @ io9_bit 1147 001b delay__temp__397select0 equ delay__temp+0 1148 001b delay__temp__397select0__byte equ delay__temp+0 1149 0001 delay__temp__397select0__bit equ 1 1150 ; expression=`{ temp @ io9_bit }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 1151 103 63b btfsc delay__temp__397select0__byte,delay__temp__397select0__bit 1152 ; if { temp @ io9_bit } body start 1153 ; Uniform delay remaining = 85 Accumulated Delay = 0 1154 ; raw_high @ 4 := 1 1155 ; Select raw_high @ 4 1156 0009 raw_high__398select0 equ raw_high+0 1157 0009 raw_high__398select0__byte equ raw_high+0 1158 0004 raw_high__398select0__bit equ 4 1159 104 589 bsf raw_high__398select0__byte,raw_high__398select0__bit 1160 ; Uniform delay remaining = 84 Accumulated Delay = 1 1161 ; Uniform delay remaining = 84 Accumulated Delay = 1 1162 ; if { temp @ io9_bit } body end 1163 ; if exp=` temp @ io9_bit ' false skip delay=2 1164 ; Other expression=`{ temp @ io9_bit }' delay=2 1165 ; if { temp @ io9_bit } end 1166 ; Uniform delay remaining = 83 Accumulated Delay = 48 1167 ; Uniform delay remaining = 83 Accumulated Delay = 48 1168 ; Process the inputs through the complements mask : 1169 ; Uniform delay remaining = 83 Accumulated Delay = 48 1170 ; previous_low := inputs_low 1171 105 20a movf inputs_low,w 1172 106 039 movwf delay__previous_low 1173 ; Uniform delay remaining = 81 Accumulated Delay = 50 1174 ; previous_high := inputs_high 1175 107 20b movf inputs_high,w 1176 108 03a movwf delay__previous_high 1177 ; Uniform delay remaining = 79 Accumulated Delay = 52 1178 ; inputs_low := {{ raw_low ^ complement_low }} & mask 1179 109 208 movf raw_low,w 1180 10a 18e xorwf complement_low,w 1181 10b e1f andlw 31 1182 10c 02a movwf inputs_low 1183 ; Uniform delay remaining = 75 Accumulated Delay = 56 1184 ; inputs_high := {{ raw_high ^ complement_high }} & mask 1185 10d 209 movf raw_high,w 1186 10e 18f xorwf complement_high,w 1187 10f e1f andlw 31 1188 110 02b movwf inputs_high 1189 ; Uniform delay remaining = 71 Accumulated Delay = 60 1190 ; Uniform delay remaining = 71 Accumulated Delay = 60 1191 ; Now generate any interrupts : 1192 ; Uniform delay remaining = 71 Accumulated Delay = 60 1193 ; temp := inputs_low & high_low | inputs_high & high_high 1194 111 20a movf inputs_low,w 1195 112 152 andwf high_low,w 1196 113 03c movwf delay__408byte0 1197 114 20b movf inputs_high,w 1198 115 153 andwf high_high,w 1199 116 11c iorwf delay__408byte0,w 1200 117 03b movwf delay__temp 1201 ; Uniform delay remaining = 64 Accumulated Delay = 67 1202 ; temp := temp | {{ inputs_low ^ mask }} & low_low | {{ inputs_high ^ mask }} & low_high 1203 118 21b movf delay__temp,w 1204 119 03c movwf delay__409byte0 1205 11a c1f movlw 31 1206 11b 18a xorwf inputs_low,w 1207 11c 150 andwf low_low,w 1208 11d 13c iorwf delay__409byte0,f 1209 11e c1f movlw 31 1210 11f 18b xorwf inputs_high,w 1211 120 151 andwf low_high,w 1212 121 11c iorwf delay__409byte0,w 1213 122 03b movwf delay__temp 1214 ; Uniform delay remaining = 53 Accumulated Delay = 78 1215 ; temp := temp | {{ inputs_low ^ previous_low }} & raising_low & inputs_low 1216 123 20a movf inputs_low,w 1217 124 199 xorwf delay__previous_low,w 1218 125 154 andwf raising_low,w 1219 126 14a andwf inputs_low,w 1220 127 13b iorwf delay__temp,f 1221 ; Uniform delay remaining = 48 Accumulated Delay = 83 1222 ; temp := temp | {{ inputs_high ^ previous_high }} & raising_high & inputs_high 1223 128 20b movf inputs_high,w 1224 129 19a xorwf delay__previous_high,w 1225 12a 155 andwf raising_high,w 1226 12b 14b andwf inputs_high,w 1227 12c 13b iorwf delay__temp,f 1228 ; Uniform delay remaining = 43 Accumulated Delay = 88 1229 ; temp := temp | {{ inputs_low ^ previous_low }} & falling_low & previous_low 1230 12d 20a movf inputs_low,w 1231 12e 199 xorwf delay__previous_low,w 1232 12f 156 andwf falling_low,w 1233 130 159 andwf delay__previous_low,w 1234 131 13b iorwf delay__temp,f 1235 ; Uniform delay remaining = 38 Accumulated Delay = 93 1236 ; temp := temp | {{ inputs_high ^ previous_high }} & falling_high & previous_high 1237 132 20b movf inputs_high,w 1238 133 19a xorwf delay__previous_high,w 1239 134 157 andwf falling_high,w 1240 135 15a andwf delay__previous_high,w 1241 136 13b iorwf delay__temp,f 1242 ; Uniform delay remaining = 33 Accumulated Delay = 98 1243 ; if { temp != 0 } start 1244 137 21b movf delay__temp,w 1245 ; expression=`{ temp != 0 }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 1246 138 743 btfss z___byte,z___bit 1247 ; if { temp != 0 } body start 1248 ; Uniform delay remaining = 33 Accumulated Delay = 0 1249 ; interrupt_pending := 1 1250 139 53e bsf interrupt_pending__byte,interrupt_pending__bit 1251 ; Uniform delay remaining = 32 Accumulated Delay = 1 1252 ; Uniform delay remaining = 32 Accumulated Delay = 1 1253 ; if { temp != 0 } body end 1254 ; if exp=` temp != 0 ' false skip delay=3 1255 ; Other expression=`{ temp != 0 }' delay=3 1256 ; if { temp != 0 } end 1257 ; Uniform delay remaining = 30 Accumulated Delay = 101 1258 ; if { receiving && interrupt_pending && interrupt_enable } start 1259 ; expression=`receiving' exp_delay=0 true_delay=10 false_delay=9 true_size=14 false_size=1 1260 13a 65e btfsc receiving__byte,receiving__bit 1261 13b b3f goto label417__4true 1262 label417__4false: 1263 ; Delay 2 cycles 1264 13c 000 nop 1265 13d 000 nop 1266 13e b4a goto and417__2false 1267 label417__4true: 1268 ; expression=`interrupt_pending' exp_delay=0 true_delay=6 false_delay=5 true_size=8 false_size=1 1269 13f 73e btfss interrupt_pending__byte,interrupt_pending__bit 1270 140 b4a goto label417__3false 1271 label417__3true: 1272 and417__2true: 1273 ; expression=`interrupt_enable' exp_delay=0 true_delay=2 false_delay=0 true_size=2 false_size=0 1274 141 71e btfss interrupt_enable__byte,interrupt_enable__bit 1275 142 b46 goto label417__1false 1276 label417__1true: 1277 and417__0true: 1278 ; if { receiving && interrupt_pending && interrupt_enable } body start 1279 ; Uniform delay remaining = 30 Accumulated Delay = 0 1280 ; serial_out := 0 1281 143 446 bcf serial_out__byte,serial_out__bit 1282 ; Uniform delay remaining = 29 Accumulated Delay = 1 1283 ; interrupt_enable := 0 1284 144 41e bcf interrupt_enable__byte,interrupt_enable__bit 1285 ; Uniform delay remaining = 28 Accumulated Delay = 2 1286 ; Uniform delay remaining = 28 Accumulated Delay = 2 1287 ; if { receiving && interrupt_pending && interrupt_enable } body end 1288 145 b49 goto label417__1end 1289 label417__1false: 1290 ; Delay 3 cycles 1291 146 000 nop 1292 147 000 nop 1293 148 000 nop 1294 ; if exp=`interrupt_enable' total delay=6 1295 ; if exp=`interrupt_enable' generic 1296 label417__1end: 1297 ; Other expression=`interrupt_enable' delay=6 1298 149 b4d goto label417__3end 1299 label417__3false: 1300 and417__2false: 1301 ; Delay 2 cycles 1302 14a 000 nop 1303 14b 000 nop 1304 14c b4d goto and417__0false 1305 ; if exp=`interrupt_pending' total delay=10 1306 ; if exp=`interrupt_pending' generic 1307 label417__3end: 1308 ; Other expression=`interrupt_pending' delay=10 1309 ; if exp=`receiving' total delay=13 1310 ; if exp=`receiving' generic 1311 label417__4end: 1312 ; Other expression=`receiving' delay=13 1313 and417__2end: 1314 and417__0false: 1315 and417__0end: 1316 ; if { receiving && interrupt_pending && interrupt_enable } end 1317 ; Uniform delay remaining = 17 Accumulated Delay = 114 1318 ; Uniform delay remaining = 17 Accumulated Delay = 114 1319 ; Soak up remaining 17 cycles 1320 ; Delay 17 cycles 1321 14d c05 movlw 5 1322 14e 03c movwf delay__344byte1 1323 delay__344delay0: 1324 14f 2fc decfsz delay__344byte1,f 1325 150 b4f goto delay__344delay0 1326 151 000 nop 1327 ; procedure delay end 1328 152 800 retlw 0 1329 ; optimize 1 1330 ; origin 0x200 1331 org 512 1332 ; bank 1 1333 ; Default register bank is now 1 1334 ; comment {The main procedure is loaded with switch statements . On the 12 - bit} 1335 ; comment {PIC ' s , switch statements have to live in the first 256 bytes of} 1336 ; comment {each code bank . For this reason , we shove main into code bank 1 .} 1337 ; comment {If we , try to put main in code bank 0 , it pushes the first bytes} 1338 ; comment {of several routines out of the first 256 bytes , which is also a} 1339 ; comment {no - no of the 12 - bit PIC ' s .} 1340 1341 ; procedure main start 1342 switch__455block_start: 1343 200 1e2 addwf pcl___register,f 1344 201 a6f goto switch__455block456 1345 202 a72 goto switch__455block460 1346 203 a75 goto switch__455block464 1347 204 a78 goto switch__455block468 1348 205 a7b goto switch__455block472 1349 206 a7e goto switch__455block476 1350 207 a81 goto switch__455block480 1351 208 a84 goto switch__455block484 1352 switch__455block_end: 1353 ; switch_check 455 switch__455block_start switch__455block_end 1354 switch__493block_start: 1355 209 1e2 addwf pcl___register,f 1356 20a a90 goto switch__493block494 1357 20b a95 goto switch__493block498 1358 20c a9a goto switch__493block502 1359 20d a9f goto switch__493block506 1360 20e aa4 goto switch__493block510 1361 20f aa9 goto switch__493block514 1362 210 aae goto switch__493block518 1363 211 ab3 goto switch__493block522 1364 switch__493block_end: 1365 ; switch_check 493 switch__493block_start switch__493block_end 1366 switch__531block_start: 1367 212 1e2 addwf pcl___register,f 1368 213 ac1 goto switch__531block532 1369 214 ac7 goto switch__531block536 1370 215 acd goto switch__531block540 1371 216 ad4 goto switch__531block544 1372 217 adb goto switch__531block548 1373 218 ae3 goto switch__531block553 1374 219 aeb goto switch__531block558 1375 21a aee goto switch__531block563 1376 switch__531block_end: 1377 ; switch_check 531 switch__531block_start switch__531block_end 1378 switch__572block_start: 1379 21b 1e2 addwf pcl___register,f 1380 21c afb goto switch__572block573 1381 21d b00 goto switch__572block577 1382 21e b05 goto switch__572block581 1383 21f b0a goto switch__572block585 1384 220 b0f goto switch__572block589 1385 221 b14 goto switch__572block593 1386 222 b19 goto switch__572block597 1387 223 b1e goto switch__572block601 1388 switch__572block_end: 1389 ; switch_check 572 switch__572block_start switch__572block_end 1390 switch__452block_start: 1391 224 1e2 addwf pcl___register,f 1392 225 a6c goto switch__452block453 1393 226 a8d goto switch__452block491 1394 227 abe goto switch__452block529 1395 228 af2 goto switch__452block569 1396 229 b23 goto switch__452block607 1397 22a b23 goto switch__452block607 1398 22b b23 goto switch__452block607 1399 22c b23 goto switch__452block607 1400 switch__452block_end: 1401 ; switch_check 452 switch__452block_start switch__452block_end 1402 switch__617block_start: 1403 22d 1e2 addwf pcl___register,f 1404 22e b30 goto switch__617block618 1405 22f b38 goto switch__617block621 1406 230 b40 goto switch__617block624 1407 231 b48 goto switch__617block627 1408 232 b50 goto switch__617block630 1409 233 b58 goto switch__617block633 1410 234 b60 goto switch__617block636 1411 235 b68 goto switch__617block639 1412 236 b70 goto switch__617block642 1413 237 b78 goto switch__617block645 1414 switch__617block_end: 1415 ; switch_check 617 switch__617block_start switch__617block_end 1416 switch__685block_start: 1417 238 1e2 addwf pcl___register,f 1418 239 ba0 goto switch__685block686 1419 23a ba0 goto switch__685block686 1420 23b ba0 goto switch__685block686 1421 23c ba0 goto switch__685block686 1422 23d ba9 goto switch__685block691 1423 23e ba9 goto switch__685block691 1424 23f baf goto switch__685block695 1425 240 baf goto switch__685block695 1426 switch__685block_end: 1427 ; switch_check 685 switch__685block_start switch__685block_end 1428 switch__702block_start: 1429 241 1e2 addwf pcl___register,f 1430 242 bb8 goto switch__702block703 1431 243 bbb goto switch__702block707 1432 244 bbe goto switch__702block711 1433 245 bc4 goto switch__702block715 1434 246 bc9 goto switch__702block719 1435 247 bd7 goto switch__702block727 1436 248 bd9 goto switch__702block731 1437 249 be0 goto switch__702block736 1438 switch__702block_end: 1439 ; switch_check 702 switch__702block_start switch__702block_end 1440 switch__660block_start: 1441 24a 1e2 addwf pcl___register,f 1442 24b b87 goto switch__660block661 1443 24c b87 goto switch__660block661 1444 24d b87 goto switch__660block661 1445 24e b87 goto switch__660block661 1446 24f b87 goto switch__660block661 1447 250 b88 goto switch__660block665 1448 251 b99 goto switch__660block679 1449 252 bb5 goto switch__660block701 1450 switch__660block_end: 1451 ; switch_check 660 switch__660block_start switch__660block_end 1452 switch__449block_start: 1453 253 1e2 addwf pcl___register,f 1454 254 a66 goto switch__449block450 1455 255 b27 goto switch__449block613 1456 256 b80 goto switch__449block654 1457 257 b81 goto switch__449block658 1458 switch__449block_end: 1459 ; switch_check 449 switch__449block_start switch__449block_end 1460 main: 1461 ; Procedure must be called with RP0, RP1, and IRP set to register bank 1 1462 ; Procedure must be called with PCLATH set to code bank 0 1463 003a main__variables__base equ global__variables__bank1+10 1464 003a main__bytes__base equ main__variables__base+0 1465 003d main__bits__base equ main__variables__base+3 1466 0004 main__total__bytes equ 4 1467 003c main__449byte0 equ main__bytes__base+2 1468 003c main__452byte0 equ main__bytes__base+2 1469 003c main__660byte0 equ main__bytes__base+2 1470 003d main__634bit1 equ main__bits__base+0 1471 003d main__634bit1__byte equ main__bits__base+0 1472 0000 main__634bit1__bit equ 0 1473 003d main__619bit1 equ main__bits__base+0 1474 003d main__619bit1__byte equ main__bits__base+0 1475 0000 main__619bit1__bit equ 0 1476 003d main__637bit1 equ main__bits__base+0 1477 003d main__637bit1__byte equ main__bits__base+0 1478 0000 main__637bit1__bit equ 0 1479 003d main__622bit1 equ main__bits__base+0 1480 003d main__622bit1__byte equ main__bits__base+0 1481 0000 main__622bit1__bit equ 0 1482 003d main__640bit1 equ main__bits__base+0 1483 003d main__640bit1__byte equ main__bits__base+0 1484 0000 main__640bit1__bit equ 0 1485 003d main__625bit1 equ main__bits__base+0 1486 003d main__625bit1__byte equ main__bits__base+0 1487 0000 main__625bit1__bit equ 0 1488 003d main__643bit1 equ main__bits__base+0 1489 003d main__643bit1__byte equ main__bits__base+0 1490 0000 main__643bit1__bit equ 0 1491 003d main__646bit1 equ main__bits__base+0 1492 003d main__646bit1__byte equ main__bits__base+0 1493 0000 main__646bit1__bit equ 0 1494 003d main__628bit1 equ main__bits__base+0 1495 003d main__628bit1__byte equ main__bits__base+0 1496 0000 main__628bit1__bit equ 0 1497 003d main__631bit1 equ main__bits__base+0 1498 003d main__631bit1__byte equ main__bits__base+0 1499 0000 main__631bit1__bit equ 0 1500 ; arguments_none 1501 003a main__command equ main__bytes__base+0 1502 003b main__temp equ main__bytes__base+1 1503 ; Initalize all of the globals : 1504 ; call reset {{ }} 1505 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1506 258 4a3 bcf pa0___byte,pa0___bit 1507 259 9ba call reset 1508 ; Process commands : 1509 ; loop_forever ... start 1510 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 1511 25a 5a3 bsf pa0___byte,pa0___bit 1512 main__444loop__forever: 1513 ; Wait for command : 1514 ; command := get_byte {{ }} 1515 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1516 25b 4a3 bcf pa0___byte,pa0___bit 1517 25c 93e call get_byte 1518 25d 214 movf get_byte__0return__byte,w 1519 25e 03a movwf main__command 1520 ; Dispatch on command : 1521 ; switch { command >> 6 } 1522 25f 39a swapf main__command,w 1523 260 03c movwf main__449byte0 1524 261 33c rrf main__449byte0,f 1525 262 31c rrf main__449byte0,w 1526 263 e03 andlw 3 1527 ; case 0 1528 ; case 1 1529 ; case 2 1530 ; case 3 1531 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1532 264 5a3 bsf pa0___byte,pa0___bit 1533 265 a53 goto switch__449block_start 1534 switch__449block450: 1535 ; < Command = 00 xx xxxx > : 1536 ; switch { {{ command >> 3 }} & 7 } 1537 266 31a rrf main__command,w 1538 267 03c movwf main__452byte0 1539 268 33c rrf main__452byte0,f 1540 269 31c rrf main__452byte0,w 1541 26a e07 andlw 7 1542 ; case 0 1543 ; case 1 1544 ; case 2 1545 ; case 3 1546 ; case 4 5 6 7 1547 26b a24 goto switch__452block_start 1548 switch__452block453: 1549 ; < Command = 0000 0 xxx > : 1550 ; switch { command & 7 } 1551 26c c07 movlw 7 1552 26d 15a andwf main__command,w 1553 ; case 0 1554 ; case 1 1555 ; case 2 1556 ; case 3 1557 ; case 4 1558 ; case 5 1559 ; case 6 1560 ; case 7 1561 26e a00 goto switch__455block_start 1562 switch__455block456: 1563 ; Read Inputs Low < Command = 0000 0000 > : 1564 ; temp := inputs_low 1565 26f 20a movf inputs_low,w 1566 270 03b movwf main__temp 1567 271 a86 goto switch__455end 1568 switch__455block460: 1569 ; Read Inputs High < Command = 0000 0001 > : 1570 ; temp := inputs_high 1571 272 20b movf inputs_high,w 1572 273 03b movwf main__temp 1573 274 a86 goto switch__455end 1574 switch__455block464: 1575 ; Read Complement Mask Low < Command = 0000 0010 > : 1576 ; temp := complement_low 1577 275 20e movf complement_low,w 1578 276 03b movwf main__temp 1579 277 a86 goto switch__455end 1580 switch__455block468: 1581 ; Read Complement Mask High < Command = 0000 0011 > : 1582 ; temp := complement_high 1583 278 20f movf complement_high,w 1584 279 03b movwf main__temp 1585 27a a86 goto switch__455end 1586 switch__455block472: 1587 ; Read Direction Mask Low < Command = 0000 0100 > : 1588 ; temp := direction_low 1589 27b 210 movf direction_low,w 1590 27c 03b movwf main__temp 1591 27d a86 goto switch__455end 1592 switch__455block476: 1593 ; Read Direction Mask High < Command = 0000 0101 > : 1594 ; temp := direction_high 1595 27e 211 movf direction_high,w 1596 27f 03b movwf main__temp 1597 280 a86 goto switch__455end 1598 switch__455block480: 1599 ; Read Raw Low < Command = 0000 0110 > : 1600 ; temp := raw_low 1601 281 208 movf raw_low,w 1602 282 03b movwf main__temp 1603 283 a86 goto switch__455end 1604 switch__455block484: 1605 ; Read Raw High < Command = 0000 0111 > : 1606 ; temp := raw_high 1607 284 209 movf raw_high,w 1608 285 03b movwf main__temp 1609 switch__455end: 1610 ; call send_byte {{ temp & mask }} 1611 286 c1f movlw 31 1612 287 15b andwf main__temp,w 1613 288 037 movwf send_byte__char 1614 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1615 289 4a3 bcf pa0___byte,pa0___bit 1616 28a 96b call send_byte 1617 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1618 28b 5a3 bsf pa0___byte,pa0___bit 1619 28c b26 goto switch__452end 1620 switch__452block491: 1621 ; < Command = 0000 1 xxx > : 1622 ; switch { command & 7 } 1623 28d c07 movlw 7 1624 28e 15a andwf main__command,w 1625 ; case 0 1626 ; case 1 1627 ; case 2 1628 ; case 3 1629 ; case 4 1630 ; case 5 1631 ; case 6 1632 ; case 7 1633 28f a09 goto switch__493block_start 1634 switch__493block494: 1635 ; Read Low Mask Low < Command = 0000 1000 > : 1636 ; temp := low_low 1637 ; Switch from register bank 1 to register bank 0 (which contains low_low) 1638 290 4a4 bcf rp0___byte,rp0___bit 1639 ; Register bank is now 0 1640 291 210 movf low_low,w 1641 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1642 292 5a4 bsf rp0___byte,rp0___bit 1643 ; Register bank is now 1 1644 293 03b movwf main__temp 1645 294 ab7 goto switch__493end 1646 switch__493block498: 1647 ; Read Low Mask High < Command = 0000 1001 > : 1648 ; temp := low_high 1649 ; Switch from register bank 1 to register bank 0 (which contains low_high) 1650 295 4a4 bcf rp0___byte,rp0___bit 1651 ; Register bank is now 0 1652 296 211 movf low_high,w 1653 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1654 297 5a4 bsf rp0___byte,rp0___bit 1655 ; Register bank is now 1 1656 298 03b movwf main__temp 1657 299 ab7 goto switch__493end 1658 switch__493block502: 1659 ; Read High Mask Low < Command = 0000 1010 > : 1660 ; temp := high_low 1661 ; Switch from register bank 1 to register bank 0 (which contains high_low) 1662 29a 4a4 bcf rp0___byte,rp0___bit 1663 ; Register bank is now 0 1664 29b 212 movf high_low,w 1665 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1666 29c 5a4 bsf rp0___byte,rp0___bit 1667 ; Register bank is now 1 1668 29d 03b movwf main__temp 1669 29e ab7 goto switch__493end 1670 switch__493block506: 1671 ; Read High Mask High < Command = 0000 1011 > : 1672 ; temp := high_high 1673 ; Switch from register bank 1 to register bank 0 (which contains high_high) 1674 29f 4a4 bcf rp0___byte,rp0___bit 1675 ; Register bank is now 0 1676 2a0 213 movf high_high,w 1677 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1678 2a1 5a4 bsf rp0___byte,rp0___bit 1679 ; Register bank is now 1 1680 2a2 03b movwf main__temp 1681 2a3 ab7 goto switch__493end 1682 switch__493block510: 1683 ; Read Raising Mask Low < Command = 0000 1100 > : 1684 ; temp := raising_low 1685 ; Switch from register bank 1 to register bank 0 (which contains raising_low) 1686 2a4 4a4 bcf rp0___byte,rp0___bit 1687 ; Register bank is now 0 1688 2a5 214 movf raising_low,w 1689 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1690 2a6 5a4 bsf rp0___byte,rp0___bit 1691 ; Register bank is now 1 1692 2a7 03b movwf main__temp 1693 2a8 ab7 goto switch__493end 1694 switch__493block514: 1695 ; Read Raising Mask High < Command = 0000 1101 > : 1696 ; temp := raising_high 1697 ; Switch from register bank 1 to register bank 0 (which contains raising_high) 1698 2a9 4a4 bcf rp0___byte,rp0___bit 1699 ; Register bank is now 0 1700 2aa 215 movf raising_high,w 1701 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1702 2ab 5a4 bsf rp0___byte,rp0___bit 1703 ; Register bank is now 1 1704 2ac 03b movwf main__temp 1705 2ad ab7 goto switch__493end 1706 switch__493block518: 1707 ; Read Falling Mask Low < Command = 0000 1110 > : 1708 ; temp := falling_low 1709 ; Switch from register bank 1 to register bank 0 (which contains falling_low) 1710 2ae 4a4 bcf rp0___byte,rp0___bit 1711 ; Register bank is now 0 1712 2af 216 movf falling_low,w 1713 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1714 2b0 5a4 bsf rp0___byte,rp0___bit 1715 ; Register bank is now 1 1716 2b1 03b movwf main__temp 1717 2b2 ab7 goto switch__493end 1718 switch__493block522: 1719 ; Read Falling Mask High < Command = 0000 1111 > : 1720 ; temp := falling_high 1721 ; Switch from register bank 1 to register bank 0 (which contains falling_high) 1722 2b3 4a4 bcf rp0___byte,rp0___bit 1723 ; Register bank is now 0 1724 2b4 217 movf falling_high,w 1725 ; Switch from register bank 0 to register bank 1 (which contains main__temp) 1726 2b5 5a4 bsf rp0___byte,rp0___bit 1727 ; Register bank is now 1 1728 2b6 03b movwf main__temp 1729 switch__493end: 1730 ; call send_byte {{ temp & mask }} 1731 2b7 c1f movlw 31 1732 2b8 15b andwf main__temp,w 1733 2b9 037 movwf send_byte__char 1734 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1735 2ba 4a3 bcf pa0___byte,pa0___bit 1736 2bb 96b call send_byte 1737 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1738 2bc 5a3 bsf pa0___byte,pa0___bit 1739 2bd b26 goto switch__452end 1740 switch__452block529: 1741 ; < Command = 0001 0 xxx > : 1742 ; switch { command & 7 } 1743 2be c07 movlw 7 1744 2bf 15a andwf main__command,w 1745 ; case 0 1746 ; case 1 1747 ; case 2 1748 ; case 3 1749 ; case 4 1750 ; case 5 1751 ; case 6 1752 ; case 7 1753 2c0 a12 goto switch__531block_start 1754 switch__531block532: 1755 ; Read Outputs Low < Command = 0001 0000 > : 1756 ; call send_byte {{ outputs_low }} 1757 2c1 20c movf outputs_low,w 1758 2c2 037 movwf send_byte__char 1759 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1760 2c3 4a3 bcf pa0___byte,pa0___bit 1761 2c4 96b call send_byte 1762 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1763 2c5 5a3 bsf pa0___byte,pa0___bit 1764 2c6 af1 goto switch__531end 1765 switch__531block536: 1766 ; Read Outputs High < Command = 0001 0001 > : 1767 ; call send_byte {{ outputs_high }} 1768 2c7 20d movf outputs_high,w 1769 2c8 037 movwf send_byte__char 1770 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1771 2c9 4a3 bcf pa0___byte,pa0___bit 1772 2ca 96b call send_byte 1773 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1774 2cb 5a3 bsf pa0___byte,pa0___bit 1775 2cc af1 goto switch__531end 1776 switch__531block540: 1777 ; Set Complement Mask Low < Command = 0001 0010 > : 1778 ; complement_low := get_byte {{ }} & mask 1779 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1780 2cd 4a3 bcf pa0___byte,pa0___bit 1781 2ce 93e call get_byte 1782 2cf 214 movf get_byte__0return__byte,w 1783 2d0 e1f andlw 31 1784 2d1 02e movwf complement_low 1785 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1786 2d2 5a3 bsf pa0___byte,pa0___bit 1787 2d3 af1 goto switch__531end 1788 switch__531block544: 1789 ; Set Complement Mask High < Command = 0001 0011 > : 1790 ; complement_high := get_byte {{ }} & mask 1791 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1792 2d4 4a3 bcf pa0___byte,pa0___bit 1793 2d5 93e call get_byte 1794 2d6 214 movf get_byte__0return__byte,w 1795 2d7 e1f andlw 31 1796 2d8 02f movwf complement_high 1797 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1798 2d9 5a3 bsf pa0___byte,pa0___bit 1799 2da af1 goto switch__531end 1800 switch__531block548: 1801 ; Set Direction Mask High < Command = 0001 0100 > : 1802 ; direction_low := get_byte {{ }} & mask 1803 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1804 2db 4a3 bcf pa0___byte,pa0___bit 1805 2dc 93e call get_byte 1806 2dd 214 movf get_byte__0return__byte,w 1807 2de e1f andlw 31 1808 2df 030 movwf direction_low 1809 ; call direction_set {{ }} 1810 2e0 99e call direction_set 1811 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1812 2e1 5a3 bsf pa0___byte,pa0___bit 1813 2e2 af1 goto switch__531end 1814 switch__531block553: 1815 ; Set Direction Mask High < Command = 0001 0101 > : 1816 ; direction_high := get_byte {{ }} & mask 1817 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1818 2e3 4a3 bcf pa0___byte,pa0___bit 1819 2e4 93e call get_byte 1820 2e5 214 movf get_byte__0return__byte,w 1821 2e6 e1f andlw 31 1822 2e7 031 movwf direction_high 1823 ; call direction_set {{ }} 1824 2e8 99e call direction_set 1825 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1826 2e9 5a3 bsf pa0___byte,pa0___bit 1827 2ea af1 goto switch__531end 1828 switch__531block558: 1829 ; Reset Everything < Command = 0001 0110 > : 1830 ; outputs_low := 0 1831 2eb 06c clrf outputs_low 1832 ; outputs_high := 0 1833 2ec 06d clrf outputs_high 1834 2ed af1 goto switch__531end 1835 switch__531block563: 1836 ; Reset Everything < Command = 0001 0110 > : 1837 ; call reset {{ }} 1838 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1839 2ee 4a3 bcf pa0___byte,pa0___bit 1840 2ef 9ba call reset 1841 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1842 2f0 5a3 bsf pa0___byte,pa0___bit 1843 switch__531end: 1844 2f1 b26 goto switch__452end 1845 switch__452block569: 1846 ; < Command = 0001 1 xxx > : 1847 ; temp := get_byte {{ }} & mask 1848 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 1849 2f2 4a3 bcf pa0___byte,pa0___bit 1850 2f3 93e call get_byte 1851 2f4 214 movf get_byte__0return__byte,w 1852 2f5 e1f andlw 31 1853 2f6 03b movwf main__temp 1854 ; switch { command & 7 } 1855 2f7 c07 movlw 7 1856 2f8 15a andwf main__command,w 1857 ; case 0 1858 ; case 1 1859 ; case 2 1860 ; case 3 1861 ; case 4 1862 ; case 5 1863 ; case 6 1864 ; case 7 1865 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 1866 2f9 5a3 bsf pa0___byte,pa0___bit 1867 2fa a1b goto switch__572block_start 1868 switch__572block573: 1869 ; Set Low Mask Low < Command = 0001 1000 > : 1870 ; low_low := temp 1871 2fb 21b movf main__temp,w 1872 ; Switch from register bank 1 to register bank 0 (which contains low_low) 1873 2fc 4a4 bcf rp0___byte,rp0___bit 1874 ; Register bank is now 0 1875 2fd 030 movwf low_low 1876 ; Switch from register bank 0 to register bank 1 1877 2fe 5a4 bsf rp0___byte,rp0___bit 1878 ; Register bank is now 1 1879 2ff b22 goto switch__572end 1880 switch__572block577: 1881 ; Set Low Mask High < Command = 0001 1001 > : 1882 ; low_high := temp 1883 300 21b movf main__temp,w 1884 ; Switch from register bank 1 to register bank 0 (which contains low_high) 1885 301 4a4 bcf rp0___byte,rp0___bit 1886 ; Register bank is now 0 1887 302 031 movwf low_high 1888 ; Switch from register bank 0 to register bank 1 1889 303 5a4 bsf rp0___byte,rp0___bit 1890 ; Register bank is now 1 1891 304 b22 goto switch__572end 1892 switch__572block581: 1893 ; Set High Mask Low < Command = 0001 1010 > : 1894 ; high_low := temp 1895 305 21b movf main__temp,w 1896 ; Switch from register bank 1 to register bank 0 (which contains high_low) 1897 306 4a4 bcf rp0___byte,rp0___bit 1898 ; Register bank is now 0 1899 307 032 movwf high_low 1900 ; Switch from register bank 0 to register bank 1 1901 308 5a4 bsf rp0___byte,rp0___bit 1902 ; Register bank is now 1 1903 309 b22 goto switch__572end 1904 switch__572block585: 1905 ; Set High Mask High < Command = 0001 1011 > : 1906 ; high_high := temp 1907 30a 21b movf main__temp,w 1908 ; Switch from register bank 1 to register bank 0 (which contains high_high) 1909 30b 4a4 bcf rp0___byte,rp0___bit 1910 ; Register bank is now 0 1911 30c 033 movwf high_high 1912 ; Switch from register bank 0 to register bank 1 1913 30d 5a4 bsf rp0___byte,rp0___bit 1914 ; Register bank is now 1 1915 30e b22 goto switch__572end 1916 switch__572block589: 1917 ; Set Raising Mask Low < Command = 0001 1100 > : 1918 ; raising_low := temp 1919 30f 21b movf main__temp,w 1920 ; Switch from register bank 1 to register bank 0 (which contains raising_low) 1921 310 4a4 bcf rp0___byte,rp0___bit 1922 ; Register bank is now 0 1923 311 034 movwf raising_low 1924 ; Switch from register bank 0 to register bank 1 1925 312 5a4 bsf rp0___byte,rp0___bit 1926 ; Register bank is now 1 1927 313 b22 goto switch__572end 1928 switch__572block593: 1929 ; Set Raising Mask High < Command = 0001 1101 > : 1930 ; raising_high := temp 1931 314 21b movf main__temp,w 1932 ; Switch from register bank 1 to register bank 0 (which contains raising_high) 1933 315 4a4 bcf rp0___byte,rp0___bit 1934 ; Register bank is now 0 1935 316 035 movwf raising_high 1936 ; Switch from register bank 0 to register bank 1 1937 317 5a4 bsf rp0___byte,rp0___bit 1938 ; Register bank is now 1 1939 318 b22 goto switch__572end 1940 switch__572block597: 1941 ; Set Falling Mask Low < Command = 0001 1110 > : 1942 ; falling_low := temp 1943 319 21b movf main__temp,w 1944 ; Switch from register bank 1 to register bank 0 (which contains falling_low) 1945 31a 4a4 bcf rp0___byte,rp0___bit 1946 ; Register bank is now 0 1947 31b 036 movwf falling_low 1948 ; Switch from register bank 0 to register bank 1 1949 31c 5a4 bsf rp0___byte,rp0___bit 1950 ; Register bank is now 1 1951 31d b22 goto switch__572end 1952 switch__572block601: 1953 ; Set Falling Mask High < Command = 0001 1111 > : 1954 ; falling_high := temp 1955 31e 21b movf main__temp,w 1956 ; Switch from register bank 1 to register bank 0 (which contains falling_high) 1957 31f 4a4 bcf rp0___byte,rp0___bit 1958 ; Register bank is now 0 1959 320 037 movwf falling_high 1960 ; Switch from register bank 0 to register bank 1 1961 321 5a4 bsf rp0___byte,rp0___bit 1962 ; Register bank is now 1 1963 switch__572end: 1964 322 b26 goto switch__452end 1965 switch__452block607: 1966 ; Set Outputs Low < Command = 001 x xxxx > : 1967 ; outputs_low := command & mask 1968 323 c1f movlw 31 1969 324 15a andwf main__command,w 1970 325 02c movwf outputs_low 1971 switch__452end: 1972 326 be3 goto switch__449end 1973 switch__449block613: 1974 ; < Command = 01 xx xxxx > : 1975 ; if { command @ 5 } start 1976 ; Alias variable for select command @ 5 1977 003a main__command__615select0 equ main__command+0 1978 003a main__command__615select0__byte equ main__command+0 1979 0005 main__command__615select0__bit equ 5 1980 ; expression=`{ command @ 5 }' exp_delay=0 true_delay=94 false_delay=3 true_size=83 false_size=3 1981 327 6ba btfsc main__command__615select0__byte,main__command__615select0__bit 1982 328 b2d goto label615__1true 1983 label615__1false: 1984 ; else body start 1985 ; Set Outputs High < Command = 010 o oooo > : 1986 ; outputs_high := command & mask 1987 329 c1f movlw 31 1988 32a 15a andwf main__command,w 1989 32b 02d movwf outputs_high 1990 ; else body end 1991 32c b7f goto label615__1end 1992 label615__1true: 1993 ; if { command @ 5 } body start 1994 ; Set Output Bit < Command = 011 v bbbb > : 1995 ; switch { command & 15 } 1996 32d c0f movlw 15 1997 32e 15a andwf main__command,w 1998 ; case 0 1999 ; case 1 2000 ; case 2 2001 ; case 3 2002 ; case 4 2003 ; case 5 2004 ; case 6 2005 ; case 7 2006 ; case 8 2007 ; case 9 2008 32f a2d goto switch__617block_start 2009 switch__617block618: 2010 ; outputs_low @ 0 := command @ 4 2011 ; Alias variable for select command @ 4 2012 003a main__command__619select2 equ main__command+0 2013 003a main__command__619select2__byte equ main__command+0 2014 0004 main__command__619select2__bit equ 4 2015 330 41d bcf main__619bit1__byte,main__619bit1__bit 2016 331 69a btfsc main__command__619select2__byte,main__command__619select2__bit 2017 332 51d bsf main__619bit1__byte,main__619bit1__bit 2018 ; Select variable outputs_low @ 0 2019 000c outputs_low__619select3 equ outputs_low+0 2020 000c outputs_low__619select3__byte equ outputs_low+0 2021 0000 outputs_low__619select3__bit equ 0 2022 333 71d btfss main__619bit1__byte,main__619bit1__bit 2023 334 40c bcf outputs_low__619select3__byte,outputs_low__619select3__bit 2024 335 61d btfsc main__619bit1__byte,main__619bit1__bit 2025 336 50c bsf outputs_low__619select3__byte,outputs_low__619select3__bit 2026 337 b7f goto switch__617end 2027 switch__617block621: 2028 ; outputs_low @ 1 := command @ 4 2029 ; Alias variable for select command @ 4 2030 003a main__command__622select2 equ main__command+0 2031 003a main__command__622select2__byte equ main__command+0 2032 0004 main__command__622select2__bit equ 4 2033 338 41d bcf main__622bit1__byte,main__622bit1__bit 2034 339 69a btfsc main__command__622select2__byte,main__command__622select2__bit 2035 33a 51d bsf main__622bit1__byte,main__622bit1__bit 2036 ; Select variable outputs_low @ 1 2037 000c outputs_low__622select3 equ outputs_low+0 2038 000c outputs_low__622select3__byte equ outputs_low+0 2039 0001 outputs_low__622select3__bit equ 1 2040 33b 71d btfss main__622bit1__byte,main__622bit1__bit 2041 33c 42c bcf outputs_low__622select3__byte,outputs_low__622select3__bit 2042 33d 61d btfsc main__622bit1__byte,main__622bit1__bit 2043 33e 52c bsf outputs_low__622select3__byte,outputs_low__622select3__bit 2044 33f b7f goto switch__617end 2045 switch__617block624: 2046 ; outputs_low @ 2 := command @ 4 2047 ; Alias variable for select command @ 4 2048 003a main__command__625select2 equ main__command+0 2049 003a main__command__625select2__byte equ main__command+0 2050 0004 main__command__625select2__bit equ 4 2051 340 41d bcf main__625bit1__byte,main__625bit1__bit 2052 341 69a btfsc main__command__625select2__byte,main__command__625select2__bit 2053 342 51d bsf main__625bit1__byte,main__625bit1__bit 2054 ; Select variable outputs_low @ 2 2055 000c outputs_low__625select3 equ outputs_low+0 2056 000c outputs_low__625select3__byte equ outputs_low+0 2057 0002 outputs_low__625select3__bit equ 2 2058 343 71d btfss main__625bit1__byte,main__625bit1__bit 2059 344 44c bcf outputs_low__625select3__byte,outputs_low__625select3__bit 2060 345 61d btfsc main__625bit1__byte,main__625bit1__bit 2061 346 54c bsf outputs_low__625select3__byte,outputs_low__625select3__bit 2062 347 b7f goto switch__617end 2063 switch__617block627: 2064 ; outputs_low @ 3 := command @ 4 2065 ; Alias variable for select command @ 4 2066 003a main__command__628select2 equ main__command+0 2067 003a main__command__628select2__byte equ main__command+0 2068 0004 main__command__628select2__bit equ 4 2069 348 41d bcf main__628bit1__byte,main__628bit1__bit 2070 349 69a btfsc main__command__628select2__byte,main__command__628select2__bit 2071 34a 51d bsf main__628bit1__byte,main__628bit1__bit 2072 ; Select variable outputs_low @ 3 2073 000c outputs_low__628select3 equ outputs_low+0 2074 000c outputs_low__628select3__byte equ outputs_low+0 2075 0003 outputs_low__628select3__bit equ 3 2076 34b 71d btfss main__628bit1__byte,main__628bit1__bit 2077 34c 46c bcf outputs_low__628select3__byte,outputs_low__628select3__bit 2078 34d 61d btfsc main__628bit1__byte,main__628bit1__bit 2079 34e 56c bsf outputs_low__628select3__byte,outputs_low__628select3__bit 2080 34f b7f goto switch__617end 2081 switch__617block630: 2082 ; outputs_low @ 4 := command @ 4 2083 ; Alias variable for select command @ 4 2084 003a main__command__631select2 equ main__command+0 2085 003a main__command__631select2__byte equ main__command+0 2086 0004 main__command__631select2__bit equ 4 2087 350 41d bcf main__631bit1__byte,main__631bit1__bit 2088 351 69a btfsc main__command__631select2__byte,main__command__631select2__bit 2089 352 51d bsf main__631bit1__byte,main__631bit1__bit 2090 ; Select variable outputs_low @ 4 2091 000c outputs_low__631select3 equ outputs_low+0 2092 000c outputs_low__631select3__byte equ outputs_low+0 2093 0004 outputs_low__631select3__bit equ 4 2094 353 71d btfss main__631bit1__byte,main__631bit1__bit 2095 354 48c bcf outputs_low__631select3__byte,outputs_low__631select3__bit 2096 355 61d btfsc main__631bit1__byte,main__631bit1__bit 2097 356 58c bsf outputs_low__631select3__byte,outputs_low__631select3__bit 2098 357 b7f goto switch__617end 2099 switch__617block633: 2100 ; outputs_high @ 0 := command @ 4 2101 ; Alias variable for select command @ 4 2102 003a main__command__634select2 equ main__command+0 2103 003a main__command__634select2__byte equ main__command+0 2104 0004 main__command__634select2__bit equ 4 2105 358 41d bcf main__634bit1__byte,main__634bit1__bit 2106 359 69a btfsc main__command__634select2__byte,main__command__634select2__bit 2107 35a 51d bsf main__634bit1__byte,main__634bit1__bit 2108 ; Select variable outputs_high @ 0 2109 000d outputs_high__634select3 equ outputs_high+0 2110 000d outputs_high__634select3__byte equ outputs_high+0 2111 0000 outputs_high__634select3__bit equ 0 2112 35b 71d btfss main__634bit1__byte,main__634bit1__bit 2113 35c 40d bcf outputs_high__634select3__byte,outputs_high__634select3__bit 2114 35d 61d btfsc main__634bit1__byte,main__634bit1__bit 2115 35e 50d bsf outputs_high__634select3__byte,outputs_high__634select3__bit 2116 35f b7f goto switch__617end 2117 switch__617block636: 2118 ; outputs_high @ 1 := command @ 4 2119 ; Alias variable for select command @ 4 2120 003a main__command__637select2 equ main__command+0 2121 003a main__command__637select2__byte equ main__command+0 2122 0004 main__command__637select2__bit equ 4 2123 360 41d bcf main__637bit1__byte,main__637bit1__bit 2124 361 69a btfsc main__command__637select2__byte,main__command__637select2__bit 2125 362 51d bsf main__637bit1__byte,main__637bit1__bit 2126 ; Select variable outputs_high @ 1 2127 000d outputs_high__637select3 equ outputs_high+0 2128 000d outputs_high__637select3__byte equ outputs_high+0 2129 0001 outputs_high__637select3__bit equ 1 2130 363 71d btfss main__637bit1__byte,main__637bit1__bit 2131 364 42d bcf outputs_high__637select3__byte,outputs_high__637select3__bit 2132 365 61d btfsc main__637bit1__byte,main__637bit1__bit 2133 366 52d bsf outputs_high__637select3__byte,outputs_high__637select3__bit 2134 367 b7f goto switch__617end 2135 switch__617block639: 2136 ; outputs_high @ 2 := command @ 4 2137 ; Alias variable for select command @ 4 2138 003a main__command__640select2 equ main__command+0 2139 003a main__command__640select2__byte equ main__command+0 2140 0004 main__command__640select2__bit equ 4 2141 368 41d bcf main__640bit1__byte,main__640bit1__bit 2142 369 69a btfsc main__command__640select2__byte,main__command__640select2__bit 2143 36a 51d bsf main__640bit1__byte,main__640bit1__bit 2144 ; Select variable outputs_high @ 2 2145 000d outputs_high__640select3 equ outputs_high+0 2146 000d outputs_high__640select3__byte equ outputs_high+0 2147 0002 outputs_high__640select3__bit equ 2 2148 36b 71d btfss main__640bit1__byte,main__640bit1__bit 2149 36c 44d bcf outputs_high__640select3__byte,outputs_high__640select3__bit 2150 36d 61d btfsc main__640bit1__byte,main__640bit1__bit 2151 36e 54d bsf outputs_high__640select3__byte,outputs_high__640select3__bit 2152 36f b7f goto switch__617end 2153 switch__617block642: 2154 ; outputs_high @ 3 := command @ 4 2155 ; Alias variable for select command @ 4 2156 003a main__command__643select2 equ main__command+0 2157 003a main__command__643select2__byte equ main__command+0 2158 0004 main__command__643select2__bit equ 4 2159 370 41d bcf main__643bit1__byte,main__643bit1__bit 2160 371 69a btfsc main__command__643select2__byte,main__command__643select2__bit 2161 372 51d bsf main__643bit1__byte,main__643bit1__bit 2162 ; Select variable outputs_high @ 3 2163 000d outputs_high__643select3 equ outputs_high+0 2164 000d outputs_high__643select3__byte equ outputs_high+0 2165 0003 outputs_high__643select3__bit equ 3 2166 373 71d btfss main__643bit1__byte,main__643bit1__bit 2167 374 46d bcf outputs_high__643select3__byte,outputs_high__643select3__bit 2168 375 61d btfsc main__643bit1__byte,main__643bit1__bit 2169 376 56d bsf outputs_high__643select3__byte,outputs_high__643select3__bit 2170 377 b7f goto switch__617end 2171 switch__617block645: 2172 ; outputs_high @ 4 := command @ 4 2173 ; Alias variable for select command @ 4 2174 003a main__command__646select2 equ main__command+0 2175 003a main__command__646select2__byte equ main__command+0 2176 0004 main__command__646select2__bit equ 4 2177 378 41d bcf main__646bit1__byte,main__646bit1__bit 2178 379 69a btfsc main__command__646select2__byte,main__command__646select2__bit 2179 37a 51d bsf main__646bit1__byte,main__646bit1__bit 2180 ; Select variable outputs_high @ 4 2181 000d outputs_high__646select3 equ outputs_high+0 2182 000d outputs_high__646select3__byte equ outputs_high+0 2183 0004 outputs_high__646select3__bit equ 4 2184 37b 71d btfss main__646bit1__byte,main__646bit1__bit 2185 37c 48d bcf outputs_high__646select3__byte,outputs_high__646select3__bit 2186 37d 61d btfsc main__646bit1__byte,main__646bit1__bit 2187 37e 58d bsf outputs_high__646select3__byte,outputs_high__646select3__bit 2188 switch__617end: 2189 ; if { command @ 5 } body end 2190 ; if exp=` command @ 5 ' generic 2191 label615__1end: 2192 ; Other expression=`{ command @ 5 }' delay=-1 2193 ; if { command @ 5 } end 2194 37f be3 goto switch__449end 2195 switch__449block654: 2196 ; < Command = 10 xx xxxx > : 2197 ; Do nothing : 2198 380 be3 goto switch__449end 2199 switch__449block658: 2200 ; < Command = 11 xx xxxx > : 2201 ; switch { {{ command >> 3 }} & 7 } 2202 381 31a rrf main__command,w 2203 382 03c movwf main__660byte0 2204 383 33c rrf main__660byte0,f 2205 384 31c rrf main__660byte0,w 2206 385 e07 andlw 7 2207 ; case 0 1 2 3 4 2208 ; case 5 2209 ; case 6 2210 ; case 7 2211 386 a4a goto switch__660block_start 2212 switch__660block661: 2213 ; < Command = 110 x xxxx or 1110 0 xxx > : 2214 ; Do nothing : 2215 387 be3 goto switch__660end 2216 switch__660block665: 2217 ; < Command = 1110 1 xxx > : 2218 ; if { command = 0xef } start 2219 388 cef movlw 239 2220 389 09a subwf main__command,w 2221 ; expression=`{ command = 0xef }' exp_delay=2 true_delay=6 false_delay=0 true_size=8 false_size=0 2222 38a 743 btfss z___byte,z___bit 2223 38b b98 goto label667__0end 2224 ; if { command = 0xef } body start 2225 ; Read Interrupt Bits < Command = 1110 1111 > : 2226 ; temporary := 0 2227 ; Switch from register bank 1 to register bank 0 (which contains temporary) 2228 38c 4a4 bcf rp0___byte,rp0___bit 2229 ; Register bank is now 0 2230 38d 078 clrf temporary 2231 ; if { interrupt_pending } start 2232 ; expression=`{ interrupt_pending }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2233 38e 63e btfsc interrupt_pending__byte,interrupt_pending__bit 2234 ; if { interrupt_pending } body start 2235 ; temporary @ 0 := 1 2236 ; Select temporary @ 0 2237 0018 temporary__671select0 equ temporary+0 2238 0018 temporary__671select0__byte equ temporary+0 2239 0000 temporary__671select0__bit equ 0 2240 38f 518 bsf temporary__671select0__byte,temporary__671select0__bit 2241 ; if { interrupt_pending } body end 2242 ; if exp=`interrupt_pending' false skip delay=2 2243 ; Other expression=`{ interrupt_pending }' delay=2 2244 ; if { interrupt_pending } end 2245 ; if { interrupt_enable } start 2246 ; expression=`{ interrupt_enable }' exp_delay=0 true_delay=1 false_delay=0 true_size=1 false_size=0 2247 390 61e btfsc interrupt_enable__byte,interrupt_enable__bit 2248 ; if { interrupt_enable } body start 2249 ; temporary @ 1 := 1 2250 ; Select temporary @ 1 2251 0018 temporary__674select0 equ temporary+0 2252 0018 temporary__674select0__byte equ temporary+0 2253 0001 temporary__674select0__bit equ 1 2254 391 538 bsf temporary__674select0__byte,temporary__674select0__bit 2255 ; if { interrupt_enable } body end 2256 ; if exp=`interrupt_enable' false skip delay=2 2257 ; Other expression=`{ interrupt_enable }' delay=2 2258 ; if { interrupt_enable } end 2259 ; call send_byte {{ temporary }} 2260 392 218 movf temporary,w 2261 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2262 393 5a4 bsf rp0___byte,rp0___bit 2263 ; Register bank is now 1 2264 394 037 movwf send_byte__char 2265 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2266 395 4a3 bcf pa0___byte,pa0___bit 2267 396 96b call send_byte 2268 ; if { command = 0xef } body end 2269 ; Switch from code bank 0 to code bank 1 before possible transfer (label) 2270 397 5a3 bsf pa0___byte,pa0___bit 2271 label667__0end: 2272 ; if exp=` command = 0xef ' empty false 2273 ; Other expression=`{ command = 0xef }' delay=-1 2274 ; if { command = 0xef } end 2275 398 be3 goto switch__660end 2276 switch__660block679: 2277 ; < Command = 1111 0 xxx > : 2278 ; Switching between register banks generates bulky code ; 2279 ; Keep code generation in bank 0 by assigning command to 2280 ; temporary : 2281 ; temporary := command 2282 399 21a movf main__command,w 2283 ; Switch from register bank 1 to register bank 0 (which contains temporary) 2284 39a 4a4 bcf rp0___byte,rp0___bit 2285 ; Register bank is now 0 2286 39b 038 movwf temporary 2287 ; switch { temporary & 7 } 2288 39c c07 movlw 7 2289 39d 158 andwf temporary,w 2290 ; case 0 1 2 3 2291 ; case 4 5 2292 ; case 6 7 2293 ; Switch from register bank 0 to register bank 1 2294 39e 5a4 bsf rp0___byte,rp0___bit 2295 ; Register bank is now 1 2296 39f a38 goto switch__685block_start 2297 switch__685block686: 2298 ; Set Interrupt Bits < Command = 1111 00 ep > : 2299 ; interrupt_enable := temporary @ 1 2300 ; Alias variable for select temporary @ 1 2301 0018 temporary__688select0 equ temporary+0 2302 0018 temporary__688select0__byte equ temporary+0 2303 0001 temporary__688select0__bit equ 1 2304 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 2305 3a0 4a4 bcf rp0___byte,rp0___bit 2306 ; Register bank is now 0 2307 3a1 41e bcf interrupt_enable__byte,interrupt_enable__bit 2308 3a2 638 btfsc temporary__688select0__byte,temporary__688select0__bit 2309 3a3 51e bsf interrupt_enable__byte,interrupt_enable__bit 2310 ; interrupt_pending := temporary @ 0 2311 ; Alias variable for select temporary @ 0 2312 0018 temporary__689select0 equ temporary+0 2313 0018 temporary__689select0__byte equ temporary+0 2314 0000 temporary__689select0__bit equ 0 2315 3a4 43e bcf interrupt_pending__byte,interrupt_pending__bit 2316 3a5 618 btfsc temporary__689select0__byte,temporary__689select0__bit 2317 3a6 53e bsf interrupt_pending__byte,interrupt_pending__bit 2318 ; Switch from register bank 0 to register bank 1 2319 3a7 5a4 bsf rp0___byte,rp0___bit 2320 ; Register bank is now 1 2321 3a8 bb4 goto switch__685end 2322 switch__685block691: 2323 ; Set Interrupt Pending < Command = 1111 010 p > : 2324 ; interrupt_pending := temporary @ 0 2325 ; Alias variable for select temporary @ 0 2326 0018 temporary__693select0 equ temporary+0 2327 0018 temporary__693select0__byte equ temporary+0 2328 0000 temporary__693select0__bit equ 0 2329 ; Switch from register bank 1 to register bank 0 (which contains interrupt_pending__byte) 2330 3a9 4a4 bcf rp0___byte,rp0___bit 2331 ; Register bank is now 0 2332 3aa 43e bcf interrupt_pending__byte,interrupt_pending__bit 2333 3ab 618 btfsc temporary__693select0__byte,temporary__693select0__bit 2334 3ac 53e bsf interrupt_pending__byte,interrupt_pending__bit 2335 ; Switch from register bank 0 to register bank 1 2336 3ad 5a4 bsf rp0___byte,rp0___bit 2337 ; Register bank is now 1 2338 3ae bb4 goto switch__685end 2339 switch__685block695: 2340 ; Set Interrupt Enable < Command = 1111 011 e > : 2341 ; interrupt_enable := temporary @ 0 2342 ; Alias variable for select temporary @ 0 2343 0018 temporary__697select0 equ temporary+0 2344 0018 temporary__697select0__byte equ temporary+0 2345 0000 temporary__697select0__bit equ 0 2346 ; Switch from register bank 1 to register bank 0 (which contains interrupt_enable__byte) 2347 3af 4a4 bcf rp0___byte,rp0___bit 2348 ; Register bank is now 0 2349 3b0 41e bcf interrupt_enable__byte,interrupt_enable__bit 2350 3b1 618 btfsc temporary__697select0__byte,temporary__697select0__bit 2351 3b2 51e bsf interrupt_enable__byte,interrupt_enable__bit 2352 ; Switch from register bank 0 to register bank 1 2353 3b3 5a4 bsf rp0___byte,rp0___bit 2354 ; Register bank is now 1 2355 switch__685end: 2356 3b4 be3 goto switch__660end 2357 switch__660block701: 2358 ; switch { command & 7 } 2359 3b5 c07 movlw 7 2360 3b6 15a andwf main__command,w 2361 ; case 0 2362 ; case 1 2363 ; case 2 2364 ; case 3 2365 ; case 4 2366 ; case 5 2367 ; case 6 2368 ; case 7 2369 3b7 a41 goto switch__702block_start 2370 switch__702block703: 2371 ; Clock Decrement < Command = 1111 1000 > : 2372 ; osccal := osccal - osccal_lsb 2373 3b8 cfc movlw 252 2374 3b9 1e5 addwf osccal,f 2375 3ba be3 goto switch__702end 2376 switch__702block707: 2377 ; Clock Increment < Command = 1111 1001 > : 2378 ; osccal := osccal + osccal_lsb 2379 3bb c04 movlw 4 2380 3bc 1e5 addwf osccal,f 2381 3bd be3 goto switch__702end 2382 switch__702block711: 2383 ; Clock Read < Command = 1111 1010 > : 2384 ; call send_byte {{ osccal }} 2385 3be 205 movf osccal,w 2386 3bf 037 movwf send_byte__char 2387 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2388 3c0 4a3 bcf pa0___byte,pa0___bit 2389 3c1 96b call send_byte 2390 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2391 3c2 5a3 bsf pa0___byte,pa0___bit 2392 3c3 be3 goto switch__702end 2393 switch__702block715: 2394 ; Clock Pulse < Command = 1111 1011 > : 2395 ; call send_byte {{ 0 }} 2396 3c4 077 clrf send_byte__char 2397 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2398 3c5 4a3 bcf pa0___byte,pa0___bit 2399 3c6 96b call send_byte 2400 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2401 3c7 5a3 bsf pa0___byte,pa0___bit 2402 3c8 be3 goto switch__702end 2403 switch__702block719: 2404 ; ID Next < Command = 1111 1100 > : 2405 ; call send_byte {{ id ~~ {{ index }} }} 2406 3c9 293 incf index,w 2407 ; Switch from register bank 1 to register bank 0 2408 3ca 4a4 bcf rp0___byte,rp0___bit 2409 ; Register bank is now 0 2410 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2411 3cb 4a3 bcf pa0___byte,pa0___bit 2412 3cc 90b call id 2413 ; Switch from register bank 0 to register bank 1 (which contains send_byte__char) 2414 3cd 5a4 bsf rp0___byte,rp0___bit 2415 ; Register bank is now 1 2416 3ce 037 movwf send_byte__char 2417 3cf 96b call send_byte 2418 ; index := index + 1 2419 3d0 2b3 incf index,f 2420 ; if { index >= id . size } start 2421 3d1 c31 movlw 49 2422 3d2 093 subwf index,w 2423 ; expression=`{ index >= id . size }' exp_delay=2 true_delay=1 false_delay=0 true_size=1 false_size=0 2424 ; Switch from code bank 0 to code bank 1 before possible transfer (btfsc) 2425 3d3 5a3 bsf pa0___byte,pa0___bit 2426 3d4 603 btfsc c___byte,c___bit 2427 ; if { index >= id . size } body start 2428 ; index := 0 2429 3d5 073 clrf index 2430 ; if { index >= id . size } body end 2431 ; if exp=` index >= id . size ' false skip delay=4 2432 ; Other expression=`{ index >= id . size }' delay=4 2433 ; if { index >= id . size } end 2434 3d6 be3 goto switch__702end 2435 switch__702block727: 2436 ; ID Reset < Command = 1111 1101 > : 2437 ; index := 0 2438 3d7 073 clrf index 2439 3d8 be3 goto switch__702end 2440 switch__702block731: 2441 ; Glitch Read < Command = 1111 1110 > : 2442 ; call send_byte {{ glitch }} 2443 3d9 212 movf glitch,w 2444 3da 037 movwf send_byte__char 2445 ; Switch from code bank 1 to code bank 0 before possible transfer (call) 2446 3db 4a3 bcf pa0___byte,pa0___bit 2447 3dc 96b call send_byte 2448 ; glitch := 0 2449 3dd 072 clrf glitch 2450 ; Switch from code bank 0 to code bank 1 before possible transfer (goto) 2451 3de 5a3 bsf pa0___byte,pa0___bit 2452 3df be3 goto switch__702end 2453 switch__702block736: 2454 ; Glitch < Command = 1111 1111 > : 2455 ; if { glitch != 0xff } start 2456 3e0 292 incf glitch,w 2457 ; expression=`{ glitch != 0xff }' exp_delay=1 true_delay=1 false_delay=0 true_size=1 false_size=0 2458 3e1 743 btfss z___byte,z___bit 2459 ; if { glitch != 0xff } body start 2460 ; glitch := glitch + 1 2461 3e2 2b2 incf glitch,f 2462 ; if { glitch != 0xff } body end 2463 ; if exp=` glitch != 0xff ' false skip delay=3 2464 ; Other expression=`{ glitch != 0xff }' delay=3 2465 ; if { glitch != 0xff } end 2466 switch__702end: 2467 switch__660end: 2468 switch__449end: 2469 3e3 a5b goto main__444loop__forever 2470 ; loop_forever ... end 2471 ; procedure main end 2472 2473 ; Register bank 0 used 22 bytes of 24 available bytes 2474 ; Register bank 1 used 14 bytes of 16 available bytes 2475 ; Register bank 2 used 0 bytes of 16 available bytes 2476 ; Register bank 3 used 0 bytes of 16 available bytes 2477 2478 end